Patent classifications
H01L21/242
Digital alloy FinFET co-integrated with passive resistor with good temperature coefficient
A method for integrating fin field effect transistors (FinFETs) and resistors on a common substrate is provided. By employing a digital alloy as a channel material for each FinFET and as a resistor body for each resistor, FinFETs with improved charge carrier mobility, and resistors with good temperature coefficient of resistance are obtained.
MULTILAYER STRUCTURE, METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR DEVICE, AND CRYSTALLINE FILM
A multilayer structure with excellent crystallinity and a semiconductor device of the multilayer structure with good mobility are provided. A multilayer structure includes: a corundum structured crystal substrate; and a crystalline film containing a corundum structured crystalline oxide as a major component, the film formed directly on the substrate or with another layer therebetween, wherein the crystal substrate has an off angle from 0.2° to 12.0°, and the crystalline oxide contains one or more metals selected from indium, aluminum, and gallium.
Multilayer structure, method for manufacturing same, semiconductor device, and crystalline film
A multilayer structure with excellent crystallinity and a semiconductor device of the multilayer structure with good mobility are provided. A multilayer structure includes: a corundum structured crystal substrate; and a crystalline film containing a corundum structured crystalline oxide as a major component, the film formed directly on the substrate or with another layer therebetween, wherein the crystal substrate has an off angle from 0.2 to 12.0, and the crystalline oxide contains one or more metals selected from indium, aluminum, and gallium.
Selective dopant junction for a group III-V semiconductor device
An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.
Ultra-high pressure doping of materials
A method and apparatus is disclosed for doping a semiconductor substrate with a dopant concentration greater than 10.sup.20 atoms per cubic centimeter. The method is suitable for producing an improved doped wide bandgap wafer for power electronic devices, photo conductive semiconductor switch, or a semiconductor catalyst.