A lateral current injection electro-optical device includes a slab having a pair of structured, doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair including an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer includes a two-dimensional photonic crystal, and a separation section extending between the pair of structured layers, the separation section separates the pair of structured layers, the separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.

A silicon photonic chip includes a silicon on insulator wafer and an electro-optical device on the silicon on insulator wafer. The electro-optical device is a lateral current injection electro-optical device that includes a slab having a pair of structured doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair of structured doped layers includes an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer is configured as a two-dimensional photonic crystal. A separation section extends between the pair of structured doped layers, the separation section fully separates the p-doped layer from the n-doped layer. The separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.

Compositions and methods for selectively removing unreacted metal material (e.g., unreacted nickel) relative to metal germanide (e.g., NiGe), metal-III-V materials, and germanium from microelectronic devices having same thereon. The compositions are substantially compatible with other materials present on the microelectronic device such as low-k dielectrics and silicon nitride.

A semiconductor device includes a substrate: a first nitride semiconductor layer formed on the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing a gallium element; a source electrode and a drain electrode formed on the second nitride semiconductor layer and contacting the second nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and containing an indium element and an aluminum element; and a gate electrode formed on the third nitride semiconductor layer and formed between the source electrode and the drain electrode.

A process of forming a HEMT that makes the contact resistance of a non-rectifying electrode consistent with other device performance is disclosed. The process includes steps of growing a GaN channel layer with a thickness smaller than 600 nm on a SiC substrate at a growth temperature lower than 1050 C. and growing an AlN spacer layer with a flow rate of NH.sub.3 at most 10% smaller than a summed flow rate of NH.sub.3 and H.sub.2. The grown GaN channel layer includes a substantial density of threading dislocations and the grown AlN layer includes a substantial density of pits.

A vertical cavity surface emitting laser includes: a supporting base: and a post including an upper distributed Bragg reflecting region, an active layer, and a lower distributed Bragg reflecting region. The upper distributed Bragg reflecting region, the active layer, and the lower distributed Bragg reflecting region are arranged on the supporting base. The lower distributed Bragg reflecting region includes first semiconductor layers and second semiconductor layers alternately arranged. The first semiconductor layers each have a refractive index lower than that of each of the second semiconductor layers. The upper distributed Bragg reflecting region includes first layers and second layers alternately arranged. The first layers each have a group III-V compound semiconductor portion and a group III oxide portion. The group III-V compound semiconductor portion contains aluminum as a group III constituent element, and the group III oxide portion surrounds the group III-V compound semiconductor portion.

A lateral current injection electro-optical device includes a slab having a pair of structured, doped layers of III-V semiconductor materials arranged side-by-side in the slab, the pair including an n-doped layer and a p-doped layer, each of the p-doped layer and the n-doped layer includes a two-dimensional photonic crystal, and a separation section extending between the pair of structured layers, the separation section separates the pair of structured layers, the separation section includes current blocking trenches, and an active region of III-V semiconductor gain materials between the current blocking trenches that form a photonic crystal cavity.

A compound semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, a channel layer formed over the compound semiconductor layer, an electron supply layer formed over the channel layer, and a source electrode, a drain electrode, and a gate electrode that are formed apart from each other over the electron supply layer. A quantum well structure is formed by the compound semiconductor layer, the channel layer, and the electron supply layer.

A process of forming a HEMT that makes the contract resistance of a non-rectifying electrode consistent with other device performance is disclosed. The process includes steps of growing a GaN channel layer with a thickness smaller than 600 nm on a SiC substrate at a growth temperature lower than 1050 C. and an AlN spacer layer with a flow rate of NH.sub.3 at most 10% smaller than a summed flow rate of NH.sub.3 and H.sub.2. The grown GaN channel layer includes substantial density of threading dislocations and the grown AlN layer includes substantial density of the pits.

A nitride high electron mobility transistor having a strain balance of an aluminum gallium nitride insertion layer is described. The transistor sequentially includes: a substrate and a GaN buffer layer located on the substrate; an AlyGa1-yN insertion layer located on the GaN buffer layer; an AlxGa1-xN barrier layer located on the AlyGa1-yN insertion layer opposite to the GaN buffer layer; a GaN cap layer located on the AlxGa1-xN barrier layer; a -shaped source electrode and drain electrode provided in recesses formed by the removal of the GaN cap layer and some thickness of the AlxGa1-xN barrier layer; and a gate electrode located between the source electrode and the drain electrode. An AlzGa1-zN insertion layer may be further included between the AlxGa1-xN barrier layer and the GaN cap layer.