A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

A silicon carbide semiconductor device includes a semiconductor substrate and a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a gate electrode provided opposing at least a surface of the second semiconductor layer between the first semiconductor region and the first semiconductor layer, across a gate insulating film; and a first electrode provided on surfaces of the first semiconductor region and the second semiconductor layer. Protons are implanted in a first region of the semiconductor substrate, spanning at least 2 μm from a surface of the semiconductor substrate facing toward the first semiconductor layer; and in a second region of the first semiconductor layer, spanning at least 3 μm from a surface of the first semiconductor layer facing toward the semiconductor substrate. The protons having a concentration in a range from 1×10.sup.13/cm.sup.3 to 1×10.sup.15/cm.sup.3.

Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement a surface-hardened EUV resist mask to pattern features in multiple layers. A layer of EUV resist material is formed on a substrate. An EUV resist mask is formed by exposing and developing the layer of EUV resist material. A surface-hardened EUV resist mask is formed by applying a surface treatment to an upper surface of the EUV resist mask to form an etch-resistant layer that is embedded in the upper surface of the EUV resist mask. At least one layer of the substrate is patterned using the surface-hardened EUV resist mask. The surface treatment can be implemented using a neutral atom beam (NAB) process which is configured to implant a chemical or metallic species into the upper surface of the EUV resist mask to form the etch-resistant layer.

A front surface element structure is formed on the front surface side of an n.sup.-type semiconductor substrate. Then defects are formed throughout an n.sup.-type semiconductor substrate to adjust a carrier lifetime. Hydrogen ions are ion-implanted from a rear surface side of the n.sup.-type semiconductor substrate, and a hydrogen implanted region having a hydrogen concentration higher than a hydrogen concentration of a bulk substrate is formed in the surface layer of a rear surface side of the n.sup.-type semiconductor substrate.

A front surface element structure is formed on the front surface side of an n.sup.-type semiconductor substrate. Then defects are formed throughout an n.sup.-type semiconductor substrate to adjust a carrier lifetime. Hydrogen ions are ion-implanted from a rear surface side of the n.sup.-type semiconductor substrate, and a hydrogen implanted region having a hydrogen concentration higher than a hydrogen concentration of a bulk substrate is formed in the surface layer of a rear surface side of the n.sup.-type semiconductor substrate.

A front surface element structure is formed on the front surface side of an n.sup.-type semiconductor substrate. Then defects are formed throughout an n.sup.-type semiconductor substrate to adjust a carrier lifetime. Hydrogen ions are ion-implanted from a rear surface side of the n.sup.-type semiconductor substrate, and a hydrogen implanted region having a hydrogen concentration higher than a hydrogen concentration of a bulk substrate is formed in the surface layer of a rear surface side of the n.sup.-type semiconductor substrate.

Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement a surface-hardened EUV resist mask to pattern features in multiple layers. A layer of EUV resist material is formed on a substrate. An EUV resist mask is formed by exposing and developing the layer of EUV resist material. A surface-hardened EUV resist mask is formed by applying a surface treatment to an upper surface of the EUV resist mask to form an etch-resistant layer that is embedded in the upper surface of the EUV resist mask. At least one layer of the substrate is patterned using the surface-hardened EUV resist mask. The surface treatment can be implemented using a neutral atom beam (NAB) process which is configured to implant a chemical or metallic species into the upper surface of the EUV resist mask to form the etch-resistant layer.

Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement a surface-hardened EUV resist mask to pattern features in multiple layers. A layer of EUV resist material is formed on a substrate. An EUV resist mask is formed by exposing and developing the layer of EUV resist material. A surface-hardened EUV resist mask is formed by applying a surface treatment to an upper surface of the EUV resist mask to form an etch-resistant layer that is embedded in the upper surface of the EUV resist mask. At least one layer of the substrate is patterned using the surface-hardened EUV resist mask. The surface treatment can be implemented using a neutral atom beam (NAB) process which is configured to implant a chemical or metallic species into the upper surface of the EUV resist mask to form the etch-resistant layer.