The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.

Embodiments described herein relate to methods forming optical device structures. One embodiment of the method includes exposing a substrate to ions at an ion angle relative to a surface normal of a surface of the substrate to form an initial depth of a plurality of depths. A patterned mask is disposed over the substrate and includes two or more projections defining exposed portions of the substrate or a device layer disposed on the substrate. Each projection has a trailing edge at a bottom surface contacting the device layer, a leading edge at a top surface of each projection, and a height from the top surface to the device layer. Exposing the substrate to ions at the ion angle is repeated to form at least one subsequent depth of the plurality of depths.

An optical image capturing system comprising, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The first lens element with negative refractive power has a concave image-side surface. The second lens element, the third lens element and the fourth lens element have refractive power. The fifth lens element has refractive power. The sixth lens element with refractive power has an image-side surface being concave in a paraxial region and includes at least one convex shape in an off-axial region, wherein the surfaces thereof are aspheric. The seventh lens element refractive power has an image-side surface being concave in a paraxial region and includes at least one convex shape in an off-axial region, wherein the surfaces thereof are aspheric.

A method of processing and passivating an implanted workpiece is disclosed, wherein, after passivation, the fugitive emissions of the workpiece are reduced to acceptably low levels. This may be especially beneficial when phosphorus, arsine, germane or another toxic species is the dopant being implanted into the workpiece. In one embodiment, a sputtering process is performed after the implantation process. This sputtering process is used to sputter the dopant at the surface of the workpiece, effectively lowering the dopant concentration at the top surface of the workpiece. In another embodiment, a chemical etching process is performed to lower the dopant concentration at the top surface. After this sputtering or chemical etching process, a traditional passivation process can be performed.

Provided is a method of manufacturing a semiconductor structure. The method includes: providing a substrate, where the substrate includes a plurality of component areas and peripheral areas surrounding the plurality of component areas; next, forming a sacrificial layer on each of the plurality of component areas, and forming a semiconductor active layer on the sacrificial layer and the substrate not covered with the sacrificial layer; patterning the semiconductor active layer to remove the semiconductor active layer on the peripheral areas so as to form a plurality of annular grooves which expose the sacrificial layer, such that the semiconductor active layer on each of the plurality of component areas is independent; afterwards, removing the sacrificial layer on each of the plurality of component areas through the annular grooves, such that the independent semiconductor active layer is separated from the substrate, where the independent semiconductor active layer forms a semiconductor structure.

The present invention provides a method for removing re-sputtered material on a substrate. A process chamber having a plasma source and a substrate support is provided along with the substrate having an upper surface and a lower surface. A masking material having a patterned sidewall is patterned onto the upper surface of the substrate along with a sacrificial layer between the upper surface of the substrate and the masking material. The lower surface of the substrate is placed onto the substrate support. A plasma is generated using the plasma source. The substrate is processed on the substrate support using the generated plasma. The sacrificial layer is removed after the processing of the substrate.

An optical image capturing system comprising, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The first lens element with negative refractive power has a concave image-side surface. The second lens element, the third lens element and the fourth lens element have refractive power. The fifth lens element has refractive power. The sixth lens element with refractive power has an image-side surface being concave in a paraxial region and includes at least one convex shape in an off-axial region, wherein the surfaces thereof are aspheric. The seventh lens element with refractive power has an image-side surface being concave in a paraxial region and includes at least one convex shape in an off-axial region, wherein the surfaces thereof are aspheric.

A method of fabricating a semiconductor device is provided. The method includes forming a first fin structure which includes first semiconductor patterns and second semiconductor patterns stacked alternately on a substrate and extends in a first direction, forming an exposed first wire pattern group which includes the second semiconductor patterns by removing the first semiconductor patterns, heat-treating the exposed first wire pattern group, and forming a first gate electrode which surrounds the first wire pattern group and extends in a second direction different from the first direction.

The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

A dielectric layer is formed on a silicon substrate. A liner layer is formed on the dielectric layer. A conductive metal layer is formed on the liner layer. A first sputter etching operation is performed on the conductive metal layer, wherein the first sputter etching operation uses a first type of etch chemistry configured to subtractively pattern the conductive metal layer for a first etching time period resulting in the remaining conductive metal layer having respective sidewalls that are not substantially vertical. A second sputter etching operation is performed on the remaining conductive metal layer, wherein the second sputter etching operation uses a second type of etch chemistry configured to further subtractively pattern the remaining conductive metal layer for a second etching time period resulting in the remaining conductive metal layer having respective sidewalls that are substantially vertical. The conductive metal layer remaining after the second sputter etching operation comprises a metal interconnect.