A semiconductor device manufacturing method of embodiments includes: performing first ion implantation implanting an element of either carbon (C) or oxygen (O) into a nitride semiconductor layer; performing second ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a coating layer on a surface of the nitride semiconductor layer; performing a first heat treatment; removing the coating layer; and performing a second heat treatment.

Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

A method of manufacturing semiconductor device of an embodiment includes performing a first ion implantation implanting at least one element selected from a group consisting of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zinc (Zn), cadmium (Cd), silicon (Si), germanium (Ge), and tin (Sn) into a nitride semiconductor layer; performing a second ion implantation implanting nitrogen (N) into the nitride semiconductor layer; performing a third ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a covering layer on a surface of the nitride semiconductor layer after the first ion implantation, the second ion implantation, and the third ion implantation; performing a first heat treatment after forming the covering layer; removing the covering layer after the first heat treatment; and performing a second heat treatment after removing the covering layer.

Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

A method of obtaining a doped semiconductor layer, including the successive steps of: a) performing, in a first single-crystal layer made of a semiconductor alloy of at least a first element A1 and a second element A2, an ion implantation of a first element B which is a dopant for the alloy and of a second element C which is not a dopant for the alloy, to make an upper portion of the first layer amorphous and to preserve the crystal structure of a lower portion of the first layer; and b) performing a solid phase recrystallization anneal of the upper portion of the first layer, resulting in transforming the upper portion of the first layer into a doped single-crystal layer of the alloy.

A method of manufacturing semiconductor device of an embodiment includes performing a first ion implantation implanting at least one element selected from a group consisting of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zinc (Zn), cadmium (Cd), silicon (Si), germanium (Ge), and tin (Sn) into a nitride semiconductor layer; performing a second ion implantation implanting nitrogen (N) into the nitride semiconductor layer; performing a third ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a covering layer on a surface of the nitride semiconductor layer after the first ion implantation, the second ion implantation, and the third ion implantation; performing a first heat treatment after forming the covering layer; removing the covering layer after the first heat treatment; and performing a second heat treatment after removing the covering layer.

A nitride semiconductor device is provide, the nitride semiconductor device including: an epitaxial layer; and an ion implantation layer that is provided on the epitaxial layer over a continuous depth range that extends over 100 nm or longer, and has a P type doping concentration equal to or higher than 110.sup.17 cm.sup.3, wherein the ion implantation layer has a region with a crystal defect density equal to or lower than 110.sup.16 cm.sup.3, the region being located in a range which is on an upper-surface-side of an interface between the epitaxial layer and the ion implantation layer, and is within 100 nm from the interface.

A method for forming a transistor device includes: implanting dopant atoms of a first doping type and dopant atoms of a second doping type into opposite sidewalls of each of a plurality of trenches of a first semiconductor layer having a basic doping of the first doping type, the dopant atoms of the first doping type having a smaller diffusion coefficient than the dopant atoms of the second doping type; filling each trench with a second semiconductor layer of the first doping type; and diffusing the dopant atoms of the first doping type and the dopant atoms of the second doping type such that a plurality of first regions of the first doping type and a plurality of second regions of the second doping type are formed. The second regions are spaced apart from each other. Each first region is at least partially arranged within a respective second region.

A group III nitride semiconductor substrate may include: a p-type conduction region into which a group II element has been implanted in a depth direction of the group III nitride semiconductor substrate from a surface of the group III nitride semiconductor substrate, the p-type conduction region having p-type conductivity, wherein hydrogen has been implanted from the p-type conduction region across an n-type conduction region adjacent to the p-type conduction region in the depth direction of the group III nitride semiconductor substrate.

A method of manufacturing a semiconductor device includes: injecting an inert element or an electron beam into a GaN-based semiconductor substrate; implanting magnesium into the GaN-based semiconductor substrate; and performing a heat treatment after the injecting and the implanting. A first implantation range of inert element or electron beam and a second implantation range of magnesium overlap with each other. A reference depth Dref (nm) calculated using a formula of Dref=D1+140 and a deepest injection depth D1 (nm) in the injecting is deeper than a deepest implantation depth D2 (nm) in the implanting. After the heat treatment, a concentration of magnesium decreases toward a deeper side at a predetermined decrease rate at a position of the reference depth Dref. The predetermined decrease rate is smaller than a decrease rate at which a concentration of magnesium becomes 1/10 per depth of 300 nm.