A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

A display apparatus and a method of manufacturing the same are provided. According to an embodiment, a display apparatus includes: a substrate; a thin-film transistor located on the substrate; and a buffer layer, a conductive layer, and an insulating layer sequentially located from the substrate between the substrate and the thin-film transistor, and a thickness of the insulating layer is less than a thickness of the buffer layer.

A pixel includes a workpiece having a protrusion and a bulk, wherein the protrusion extends from an upper surface of the bulk. The pixel further includes a protrusion doping region in the protrusion. The pixel further includes a photosensitive device comprising a plurality of first regions, wherein each of the plurality of first regions is in the bulk and the protrusion.

A method can include ion implanting with the gate mask to form first halo regions and ion implanting with the gate mask and first spacers as a mask to form second halo regions. The gate mask and first spacers can be removed, and an epitaxial layer formed. A dummy gate mask can be formed. Ion implanting with the dummy gate mask can from source-drain extensions. Second spacers can be formed on sides of the dummy gate mask. Ion implanting with the dummy gate mask and second spacers as a mask can form source and drain regions. A surface dielectric layer can be formed and planarized to expose a top of the dummy gate. The dummy gate can be removed to form gate openings between the second spacers. A hi-K dielectric layer and at least two gate metal layers within the gate opening. Related devices are also disclosed.

A method can include ion implanting with the gate mask to form first halo regions and ion implanting with the gate mask and first spacers as a mask to form second halo regions. The gate mask and first spacers can be removed, and an epitaxial layer formed. A dummy gate mask can be formed. Ion implanting with the dummy gate mask can from source-drain extensions. Second spacers can be formed on sides of the dummy gate mask. Ion implanting with the dummy gate mask and second spacers as a mask can form source and drain regions. A surface dielectric layer can be formed and planarized to expose a top of the dummy gate. The dummy gate can be removed to form gate openings between the second spacers. A hi-K dielectric layer and at least two gate metal layers within the gate opening. Related devices are also disclosed.

A preparation method for a flat cell ROM device, comprising the steps of: providing a substrate, and forming a P well on the substrate; forming a photomask layer on the P well and performing photoetching to form an injection window; injecting P-type ions in the formed injection window to form a P-type region; injecting N-type ions in the injection window so as to form an N-type region on the P-type region; and forming a gate oxide layer and a poly-silicon gate so as to complete the preparation of a device.

A preparation method for a flat cell ROM device, comprising the steps of: providing a substrate, and forming a P well on the substrate; forming a photomask layer on the P well and performing photoetching to form an injection window; injecting P-type ions in the formed injection window to form a P-type region; injecting N-type ions in the injection window so as to form an N-type region on the P-type region; and forming a gate oxide layer and a poly-silicon gate so as to complete the preparation of a device.

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

A semiconductor device is manufactured by: i) forming a mask on a process surface of a semiconductor layer, elongated openings of the mask exposing part of the semiconductor layer and extending along a first lateral direction; ii) implanting dopants of a first conductivity type into the semiconductor layer based on tilt angle α1 between an ion beam direction and a process surface normal and based on twist angle ω1 between the first lateral direction and a projection of the ion beam direction on the process surface; iii) implanting dopants of a second conductivity type into the semiconductor layer based on tilt angle α2 between an ion beam direction and the process surface normal and based on twist angle ω2 between the first lateral direction and a projection of the ion beam direction on the process surface; and repeating i) to iii) at least one time.