Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

The present disclosure is directed to a diode with a semiconductor body of silicon including a cathode region, which has a first conductivity type and is delimited by a front surface; and an anode region, which has a second conductivity type and extends into the cathode region from the front surface. The diode further includes a barrier region of cobalt disilicide, arranged on the anode region; and a metallization region of aluminum or of an aluminum alloy, arranged on the barrier region. The barrier region contacts the anode region.

A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.

A junction barrier Schottky diode device and a method for fabricating the same is disclosed. In the junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.

A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.

Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.

Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.