Patent classifications
H01L21/288
EDGE REMOVAL FOR THROUGH-RESIST PLATING
An electroplating cup assembly comprises a cup bottom, a lip seal, and an electrical contact structure. The cup bottom at least partially defines an opening configured to allow exposure of a wafer positioned in the cup assembly to an electroplating solution. The lip seal is on the cup bottom and comprises a sealing structure extending upwardly along an inner edge of the lip seal to a peak that is configured to be in contact with a seed layer of a wafer and adjacent to a sacrificial layer of the wafer. The electrical contact structure is over a portion of the seal. The electrical contact structure configured to be coupled to the seed layer of the wafer.
STRUCTURE AND METHOD FOR IMPROVED STABILIZATION OF COBALT CAP AND/OR COBALT LINER IN INTERCONNECTS
A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
STRUCTURE AND METHOD FOR IMPROVED STABILIZATION OF COBALT CAP AND/OR COBALT LINER IN INTERCONNECTS
A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
Semiconductor device and method of forming micro interconnect structures
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
Semiconductor device and method of forming micro interconnect structures
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
Acoustic measurement of fabrication equipment clearance
Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
Acoustic measurement of fabrication equipment clearance
Methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (IC) processing system and/or determine a thickness of a material layer of the wafer during IC processing implemented by the IC processing system. An exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. The substrate is positioned within an IC processing system. The method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. The electrical signals indicate a thickness of the material layer.
HIGH RESISTIVITY IRON-BASED, THERMALLY STABLE MAGNETIC MATERIAL FOR ON-CHIP INTEGRATED INDUCTORS
An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.
HIGH RESISTIVITY IRON-BASED, THERMALLY STABLE MAGNETIC MATERIAL FOR ON-CHIP INTEGRATED INDUCTORS
An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.
METHOD OF CONTROLLING CHEMICAL CONCENTRATION IN ELECTROLYTE
A method of controlling chemical concentration in electrolyte includes measuring a chemical concentration in an electrolyte, wherein the electrolyte is contained in a tank; and increasing a vapor flux through an exhaust pipe connected to the tank when the measured chemical concentration is lower than a control lower limit value.