An electroplating apparatus for electroplating metal on a substrate includes a plating chamber configured to contain an electrolyte, a substrate holder configured to hold and rotate the substrate during electroplating, an anode, and an azimuthally asymmetric auxiliary electrode configured to be biased both anodically and cathodically during electroplating. The azimuthally asymmetric auxiliary electrode (which may be, for example, C-shaped), can be used for controlling azimuthal uniformity of metal electrodeposition by donating and diverting ionic current at a selected azimuthal position. In another aspect, an electroplating apparatus for electroplating metal includes a plating chamber configured to contain an electrolyte, a substrate holder configured to hold and rotate the substrate during electroplating, an anode, a shield configured to shield current at the periphery of the substrate; and an azimuthally asymmetric auxiliary anode configured to donate current to the shielded periphery of the substrate at a selected azimuthal position on the substrate.

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Nanotwinned copper and non-nanotwinned copper may be electroplated to form mixed crystal structures such as 2-in-1 copper via and RDL structures or 2-in-1 copper via and pillar structures. Nanotwinned copper may be electroplated on a non-nanotwinned copper layer by pretreating a surface of the non-nanotwinned copper layer with an oxidizing agent or other chemical reagent. Alternatively, nanotwinned copper may be electroplated to partially fill a recess in a dielectric layer, and non-nanotwinned copper may be electroplated over the nanotwinned copper to fill the recess. Copper overburden may be subsequently removed.

An electrolytic processing jig configured to perform an electrolytic processing on a processing target substrate includes a base body having a flat plate shape; an electrode provided at the base body; three or more terminals provided at the base body, each having elasticity and configured to be brought into contact with a peripheral portion of the processing target substrate; and a detecting unit configured to electrically detect a contact of at least one of the terminals with the processing target substrate.

An interconnect structure of a semiconductor device includes a conductive via and a barrier layer lining an interface between a dielectric layer and the conductive via. The barrier layer is selectively deposited along sidewalls of a recess formed in a dielectric layer. The conductive via is formed by selectively electroplating electrically conductive material such as rhodium, iridium, or platinum in an opening of the recess, where the conductive via is grown upwards from an exposed metal surface at a bottom of the recess. The conductive via includes an electrically conductive material having a low electron mean free path, low electrical resistivity, and high melting point. The interconnect structure of the semiconductor device has reduced via resistance and improved resistance to electromigration and/or stress migration.

Undesired deposition of metals on a lipseal (lipseal plate-out) during electrodeposition of metals on semiconductor substrates is minimized or eliminated by minimizing or eliminating ionic current directed at a lipseal. For example, electrodeposition can be conducted such as to avoid contact of a lipseal with a cathodically biased conductive material on the semiconductor substrate during the course of electroplating. This can be accomplished by shielding a small selected zone proximate the lipseal to suppress electrode-position of metal proximate the lipseal, and to avoid contact of metal with a lipseal. In some embodiments shielding is accomplished by sequentially using lipseals of different inner diameters during electroplating of metals into through-resist features, where a lipseal having a smaller diameter is used during a first electroplating step and serves as a shield blocking electrodeposition in a selected zone. In a second electroplating step, a lipseal of a larger inner diameter is used.

Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR.sup.1R.sup.2R.sup.3H.sup.+).sub.nX.sup.n−, wherein R.sup.1, R.sup.2, R.sup.3 are independently H or linear or branched C.sub.1 to C.sub.6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.

A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.