A method of splitting off a semiconductor wafer from a semiconductor bottle includes: forming a separation region within the semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule.

A method of processing a wafer having a plurality of devices formed in respective areas on a face side of the wafer, the areas being demarcated by a plurality of intersecting projected dicing lines, includes a low-viscosity resin applying step of coating the face side of the wafer with a first liquid resin of low viscosity to cover an area of the wafer where the plurality of devices are present, a high-viscosity resin applying step of, after the low-viscosity resin applying step, coating the face side of the wafer with a second liquid resin of higher viscosity than the first liquid resin in overlapping relation to the first liquid resin, a resin curing step of curing the first liquid resin and the second liquid resin that have coated the face side of the wafer into a protective film, and a planarizing step of planarizing the protective film.

Provided is a semiconductor device including: a semiconductor substrate provided with an active portion and an edge termination structure portion surrounding the active portion; an interlayer dielectric film provided above the semiconductor substrate; a protective film provided above the interlayer dielectric film; and a protruding portion provided farther from the active portion than the edge termination structure portion and protruding further than the interlayer dielectric film. The protruding portion is not covered with the protective film. The protective film is provided closer to the active portion than the protruding portion.

A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.

A superstrate for planarizing a substrate. The superstrate includes a body having a first side having a contact surface and a second side having a central portion and a peripheral portion surrounding the central portion. The peripheral portion includes a recessed region.

Ultra-compact inductor devices for use in integrated circuits (e.g., RF ICs) that use 3-dimensional Dirac materials for providing the inductor. Whereas inductors currently require significant real estate on an integrated circuit, because they require use of an electrically conductive winding around an insulative core, or such metal deposited in a spiral geometry, the present devices can be far more compact, occupying significantly less space on an integrated circuit. For example, an ultra-compact inductor that could be included in an integrated circuit may include a 3-dimensional Dirac material formed into a geometric shape capable of inductance (e.g., as simple as a stripe or series of stripes of such material), deposited on a substantially non-conductive (i.e., insulative) substrate, on which the Dirac material in the selected geometric shape is positioned. Low temperature manufacturing methods compatible with CMOS manufacturing are also provided.

A novel dielectric cap structure for VTFET device fabrication is provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a substrate using fin hardmasks, including a first fin(s) and a second fin(s); depositing a liner over the fins and the fin hardmasks; selectively forming first hardmask caps on top of the fin hardmasks/liner over the first fin(s); forming first bottom source and drain at a base of the first fin(s) while the fin hardmasks/liner over the first fin(s) are preserved by the first hardmask caps; selectively forming second hardmask caps on top of the fin hardmasks/liner over the second fin(s); and forming second bottom source and drains at a base of the second fin(s) while the fin hardmasks/liner over the second fin(s) are preserved by the second hardmask caps. A device structure is also provided.

A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

The present invention provides a film forming method of forming a film on a substrate, wherein the substrate includes a region including a first concave portion and a second concave portion, the first concave portion has a width larger than that of the second concave portion, and the film forming method includes: selectively supplying a first material into the first concave portion and molding the first material; and supplying a second material onto the region and molding the second material, such that the second concave portion is filled with the second material and a planarization film of the second material is formed over all of the region.

Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.