Disclosed is a method for manufacturing a semiconductor device. The method includes: forming a gate insulating material layer on a substrate; forming a gate material layer on the gate insulating material layer; and performing an etching process on the gate material layer and the gate insulating material layer to form a gate layer and a gate insulating layer. The gate insulating layer and the gate layer each include a first end and a second end opposite to each other in a direction parallel to a channel length. The first end of the gate insulating layer is recessed inwards by a preset length relative to the first end of the gate layer, and the second end of the gate insulating layer is recessed inwards by the preset length relative to the second end of the gate layer.

Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

A method for forming etched features in a layer of a first material is provided. A layer of a second material is deposited over the layer of the first material. An alloy layer of the first material and the second material is formed between the layer of the first material and the layer of the second material. The layer of the first material is selectively etched with respect to the alloy layer, using the alloy layer as a hardmask.

A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

A semiconductor process system includes a process chamber with a lid. The system includes a heater positioned on the lid and a controller configured to control the heater. The controller operates the heater to provide a selected temperature distribution of the lid.

Embodiments of the present disclosure relates to method of forming trench and via features using dielectric and metal mask layers. Particularly, embodiments of present disclosure provide a hard mask stack including a first dielectric mask layer, and second dielectric mask layer and a metal mask layer, wherein the first dielectric mask layer and second dielectric mask layer have a high etch selectivity.

Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first etch stop layer from a portion of a gate mask, the gate mask extending between spacers adjacent a gate electrode, the gate electrode overlying a semiconductor fin. The method further includes forming a second etch stop layer adjacent the first etch stop layer, forming an opening through the second etch stop layer, and exposing the first etch stop layer by performing a first etching process. The method further includes extending the opening through the first etch stop layer and exposing the gate electrode by performing a second etching process. Once the gate electrode has been exposed, the method further includes forming a gate contact in the opening.

A method of forming a via is provided. A lower metal element is formed, and a first patterned photoresist is used to form a sacrificial element over the lower metal element. A dielectric region including a dielectric element projection extending upwardly above the sacrificial element is formed. A second patterned photoresist including a second photoresist opening is formed, wherein the dielectric element projection is at least partially located in the second photoresist opening. A dielectric region trench opening is etched in the dielectric region. The sacrificial element is removed to define a via opening extending downwardly from the dielectric region trench opening. The dielectric region trench opening and the via opening are filled to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.

Embodiments of the present application relate to the field of semiconductors, and provide a manufacturing method of a semiconductor structure and a structure thereof. The method of manufacturing a semiconductor structure includes: providing a substrate, active regions and an isolation structure; patterning the active regions and the isolation structure to form a word line trench, sidewalls of the word line trench exposing the active regions and the isolation structure; performing corner rounding at least once on the active regions and the isolation structure exposed by the sidewalls of the word line trench, such that a first height difference is formed between remaining active regions and the isolation structure, wherein the corner rounding includes: etching the isolation structure exposed by the sidewalls of the word line trench, such that a first thickness of the active regions are exposed by the isolation structure.