Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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21/00
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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H01L21/02
Manufacture or treatment of semiconductor devices or of parts thereof
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H01L21/04
the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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H01L21/18
the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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H01L21/30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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H01L21/31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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H01L21/316
composed of oxides or glassy oxides or oxide based glass
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H01L21/31654
of semiconductor materials, e.g. the body itself
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H01L21/31654

Methods of forming a semiconductor device by thermally treating a cleaned surface of a semiconductor substrate in a non-oxidizing ambient
09799523 · 2017-10-24 · ·

The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å.