In one embodiment, a semiconductor device includes a stacked film alternately including a plurality of electrode layers and a plurality of insulating layers. The device further includes a first insulator, a charge storage layer, a second insulator and a first semiconductor layer that are disposed in order in the stacked film. The device further includes a plurality of first films disposed between the first insulator and the plurality of insulating layers. Furthermore, at least one of the first films includes a second semiconductor layer.

This disclosure relates to a composition that includes at least one first ruthenium removal rate enhancer; at least one copper removal rate inhibitor; at least one low-k removal rate inhibitor; and an aqueous solvent.

A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.

Provided are a polishing device including: a surface plate; a polishing pad mounted on the surface plate; a carrier for accommodating a polishing object; and a slurry supply unit including at least one nozzle, wherein the carrier performs a vibrating motion in a trajectory from the center of the surface plate to the end of the surface plate, and the slurry supply unit performs a vibrating motion at the same trajectory and speed as those of the vibrating motion of the carrier, as a polishing device which includes a slurry supply unit enabling subdivided driving in the supply of a polishing slurry, and in which the driving of the slurry supply unit has an advantage enabling optimized driving in an organic relationship between rotation and/or vibrating motion of the carrier and the surface plate and vertical pressurization conditions, etc. for the polishing surface of the carrier.

A variety of applications can include apparatus having a memory device with an array of vertical strings of memory cells for the memory device with data lines coupled to the vertical strings, where the data lines have been formed by a metal liner deposition process. In the metal liner deposition, a metal can be formed on a patterned dielectric region. The metal liner deposition process allows for construction of the height of the data lines to be well controlled with selection of a thickness for the dielectric region used in forming the metal liner. Use of a metal liner deposition provides a controlled mechanism to reduce data line capacitance by being able to select liner thickness in forming the data lines. The use of the dielectric region with the metal liner deposition can allow the fabrication of the data lines to avoid pitch double or pitch quad processes.

The invention provides a method for polishing or planarizing a substrate of at least one of semiconductor, optical and magnetic substrates. The method includes attaching a polymer-polymer composite polishing pad having a polishing layer to a polishing device. A hydrophilic polymeric matrix forms the polishing layer. Cationic fluoropolymer particles having nitrogen-containing end groups are embedded in the polymeric matrix. A slurry containing anionic particles is applied to the polymer-polymer composite polishing pad and rubbed against the substrate to polish or planarize the substrate with the fluoropolymer particles interacting with the anionic particles to increase polishing removal rate.

A manufacturing system performs a deposition of an etch-compatible film over a substrate. The etch-compatible film includes a first surface and a second surface opposite to the first surface. The manufacturing system performs a partial removal of the etch-compatible film to create a surface profile on the first surface with a plurality of depths relative to the substrate. The manufacturing system performs a deposition of a second material over the profile created in the etch-compatible film. The manufacturing system performs a planarization of the second material to obtain a plurality of etch heights of the second material in accordance with the plurality of depths in the profile created in the etch-compatible film. The manufacturing system performs a lithographic patterning of a photoresist deposited over the planarized second material to obtain the plurality of etch heights and one or more duty cycles in the second material.

Provided is a polishing composition for a semiconductor process comprising abrasive particles, the abrasive particles containing an amine-based polishing rate improver, and comprising the amine-based polishing rate improver. Provided is a polishing composition for a semiconductor process further comprising an amine-based surface modifier around the surface of the abrasive particles, wherein the sum of the content of an amine group contained in the amine-based polishing rate improver and the content of an amine group contained in the amine-based surface modifier is 0.0185% by weight or more based on the total composition weight. The polishing composition for a semiconductor process may implement the polishing rate and defect prevention performance within a target range in polishing the boron-doped polysilicon layer.

A barrier chemical mechanical planarization polishing composition is provided that includes suitable chemical additives. The suitable chemical additives are silicate compound and high molecular weight polymers/copolymers. There is also provided a chemical mechanical polishing method using the barrier chemical mechanical planarization polishing composition.

6T-SRAM cell designs for larger SRAM arrays and methods of manufacture generally include a single fin device for both nFET (pass-gate (PG) and pull-down (PD)) and pFET (pull-up (PU). The pFET can be configured with a smaller effective channel width (Weff) than the nFET or with a smaller active fin height. An SRAM big cell consumes the (111) 6t-SRAM design area while provide different Weff ratios other than 1:1 for PU/PD or PU/PG as can be desired for different SRAM designs.