Patent classifications
H01L21/326
BREAKDOWN-BASED PHYSICAL UNCLONABLE FUNCTION
A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.
BREAKDOWN-BASED PHYSICAL UNCLONABLE FUNCTION
A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.
Methods and apparatus for test pattern forming and film property measurement
A method for electrically characterizing a layer disposed on a substrate and electrically insulated from the substrate is disclosed. The method can include forming a test pattern, contacting the test pattern with electrical contact elements at contact regions, and measuring an electrical parameter of the layer by passing a first set of test currents between contact regions. The test pattern can be formed by pushing a pattern forming head against a top surface of the layer, introducing a first fluid into the cavity, and converting the sacrificial portion of the layer into an insulator using the first fluid and forming the test pattern under the test-pattern-shaped inner seal.
Methods and apparatus for test pattern forming and film property measurement
A method for electrically characterizing a layer disposed on a substrate and electrically insulated from the substrate is disclosed. The method can include forming a test pattern, contacting the test pattern with electrical contact elements at contact regions, and measuring an electrical parameter of the layer by passing a first set of test currents between contact regions. The test pattern can be formed by pushing a pattern forming head against a top surface of the layer, introducing a first fluid into the cavity, and converting the sacrificial portion of the layer into an insulator using the first fluid and forming the test pattern under the test-pattern-shaped inner seal.
Plasma annealing method and device for the same
There is provided a plasma annealing device that can change the crystal structure of a film by processing the film (coating) on a substrate and that has excellent productivity. A method for producing a film includes step (A) irradiating a film on a substrate with atmospheric pressure plasma, wherein the crystal structure of a constituent of the film is changed. The step (A) may include generating plasma under atmospheric pressure by energization at a frequency of 10 hertz to 100 megahertz and a voltage of 60 volts to 1,000,000 volts, and directly irradiating the film on the substrate with the generated plasma. A method for changing a crystal structure of a constituent of a film includes step (A). A plasma generation device used in step (A). An electronic device produced through step (A).
Plasma annealing method and device for the same
There is provided a plasma annealing device that can change the crystal structure of a film by processing the film (coating) on a substrate and that has excellent productivity. A method for producing a film includes step (A) irradiating a film on a substrate with atmospheric pressure plasma, wherein the crystal structure of a constituent of the film is changed. The step (A) may include generating plasma under atmospheric pressure by energization at a frequency of 10 hertz to 100 megahertz and a voltage of 60 volts to 1,000,000 volts, and directly irradiating the film on the substrate with the generated plasma. A method for changing a crystal structure of a constituent of a film includes step (A). A plasma generation device used in step (A). An electronic device produced through step (A).
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
A semiconductor device manufacturing method of embodiments includes: performing first ion implantation implanting an element of either carbon (C) or oxygen (O) into a nitride semiconductor layer; performing second ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a coating layer on a surface of the nitride semiconductor layer; performing a first heat treatment; removing the coating layer; and performing a second heat treatment.
Integrated circuit with P-N-P junction and vertically aligned field effect transistor, and method to form same
Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a p-type substrate, a p-well region within the p-type substrate, and an n-type barrier region between the p-type substrate and the p-well region. The n-type barrier region physically isolates the p-type substrate from the p-well region. A field effect transistor (FET) is positioned above the p-well region, and a buried insulator layer on the upper surface of the p-well region separates the transistor from the p-well region. A first voltage source electrically coupled to the p-well region induces a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate.
Integrated circuit with P-N-P junction and vertically aligned field effect transistor, and method to form same
Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a p-type substrate, a p-well region within the p-type substrate, and an n-type barrier region between the p-type substrate and the p-well region. The n-type barrier region physically isolates the p-type substrate from the p-well region. A field effect transistor (FET) is positioned above the p-well region, and a buried insulator layer on the upper surface of the p-well region separates the transistor from the p-well region. A first voltage source electrically coupled to the p-well region induces a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes preparing a substrate including cell regions and a scribe lane region, forming circuit blocks in the cell regions of the substrate, the substrate including a first surface and a second surface, forming a bias pad on the first surface of the substrate, such that the bias pad is in the scribe lane region of the substrate, bonding a deuterium exchange structure to the second surface of the substrate, implanting deuterium into the deuterium exchange structure using plasma processing, and applying a first voltage to the bias pad, such that the deuterium is diffused from the deuterium exchange structure into the substrate through the second surface of the substrate.