An IGZO thin-film transistor and a method for manufacturing same. The method comprises: acquiring a substrate; forming an IGZO layer on the substrate by means of a solution process; doping V impurities on a surface of the IGZO layer by means of a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side thereof; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.

This disclosure provides a display device, an array substrate, a thin film transistor and a fabrication method thereof. The thin film transistor includes an active layer, a gate insulating layer, a gate electrode, a dielectric layer, a source electrode and a drain electrode. The active layer has a channel region, doped regions at both sides of the channel region, and buffer regions each of which arranged between the corresponding doped region and the channel region, and a doping concentration of the buffer regions is less than that of the doped regions. The gate insulating layer is at a side of the active layer, covers the channel region and the buffer regions, and exposes the doped regions. The gate electrode is on a surface of the gate insulating layer facing away from the active layer.

The present disclosure relates to a metal oxide TFT and the manufacturing method thereof. The TFT includes a substrate, a buffering layer formed on the substrate, and an active layer formed on the buffering layer. The TFT further includes a source and a drain formed at two lateral sides of the active layer, a gate insulation layer formed on the active layer, a gate formed on the gate insulation layer, and an dielectric layer formed on the gate. The dielectric layer is made by SiOx. The dielectric layer is made by SiOx, instead of SiNx, wherein the content of the hydrogen ion may be lower. Thus, the hydrogen ion may be prevented from being diffused within the active layer so as to avoid the huge electrical leakage, which enhances the electrical performance of the metal oxide TFT.

The present disclosure relates to a metal oxide TFT and the manufacturing method thereof. The TFT includes a substrate, a buffering layer formed on the substrate, and an active layer formed on the buffering layer. The TFT further includes a source and a drain formed at two lateral sides of the active layer, a gate insulation layer formed on the active layer, a gate formed on the gate insulation layer, and an dielectric layer formed on the gate. The dielectric layer is made by SiOx. The dielectric layer is made by SiOx, instead of SiNx, wherein the content of the hydrogen ion may be lower. Thus, the hydrogen ion may be prevented from being diffused within the active layer so as to avoid the huge electrical leakage, which enhances the electrical performance of the metal oxide TFT.

A semiconductor device includes a transistor which includes a first gate electrode, a first insulating film, an oxide semiconductor film, source and drain electrodes, a second insulating film, and a second gate electrode. The oxide semiconductor film includes a first oxide semiconductor film in contact with the first insulating film, a second oxide semiconductor film in contact with the first oxide semiconductor film, and a third oxide semiconductor film in contact with the second oxide semiconductor film. The first to third oxide semiconductor films each contain In, Zn, and M (M represents Al, Ga, Y, or Sn). The third oxide semiconductor film includes a region in contact with a side surface of the second oxide semiconductor film and a region in contact with the second insulating film. The third oxide semiconductor film includes a region where the content of M is greater than or equal to that of In.

A thin film transistor and a producing method thereof, and an array substrate, which belong to a technical field of the thin film transistor, can solve a problem of poor performance of a conventional thin film transistor. The producing method of the thin film transistor comprises: S1: forming a gate electrode (11) composed of graphene; S2: forming a gate insulating layer (12) composed of oxidized graphene; S3: forming an active region (13) composed of doped oxidized graphene or doped graphene; S4: forming a source electrode (14) and a drain electrode (15) composed of graphene, wherein, the graphene composing the source electrode (14), the drain electrode (15) and the gate electrode (11) is formed by reducing oxidized graphene, and the doped oxidized graphene or doped graphene composing the active region (13) is formed by treating oxidized graphene.

A method for forming a semiconductor device includes incorporating dopants of a first conductivity type into a nearby body region portion of a semiconductor substrate having a base doping of the first conductivity type. The incorporation of the dopants of the first conductivity type is masked by a mask structure at at least part of an edge region of the semiconductor substrate. The method further includes forming a body region of a transistor structure of a second conductivity type in the semiconductor substrate. The nearby body region portion of the semiconductor substrate is located adjacent to the body region of the transistor structure.