A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.

A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

An array substrate, a fabrication method thereof, and a display panel are provided. The array substrate comprises a substrate, and a plurality of thin-film-transistors, which includes an active layer formed on the substrate including a source region, a drain region, and a channel region located between the source region and the drain region, a source electrode metal contact layer, a drain electrode metal contact layer, a barrier layer formed on a side of the active layer facing away from the substrate, a source electrode formed on a side of the source electrode metal contact layer facing away from active layer, a drain electrode formed on a side of the drain electrode metal contact layer facing away from the active layer, and a gate electrode insulated from the barrier layer and formed on a side of the barrier layer facing away from the active layer.

An array substrate, a fabrication method thereof, and a display panel are provided. The array substrate comprises a substrate, and a plurality of thin-film-transistors, which includes an active layer formed on the substrate including a source region, a drain region, and a channel region located between the source region and the drain region, a source electrode metal contact layer, a drain electrode metal contact layer, a barrier layer formed on a side of the active layer facing away from the substrate, a source electrode formed on a side of the source electrode metal contact layer facing away from active layer, a drain electrode formed on a side of the drain electrode metal contact layer facing away from the active layer, and a gate electrode insulated from the barrier layer and formed on a side of the barrier layer facing away from the active layer.

A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate.

A 3D-NAND memory includes a transistor formed in a first side of a periphery circuit substrate, a memory cell stack formed over a first side of a cell array substrate, and a first connection structure formed over an opposing second side of the cell array substrate. The memory cell stack includes a doped region formed in the first side of the cell array substrate and coupled to the first connection structure through a first VIA, a common source structure that extends from the doped region toward the first side of the periphery circuit substrate, and a second connection structure that is positioned over and coupled to the common source structure. The first side of the cell array substrate and the first side of the periphery circuit substrate are aligned facing each other so that the transistor is coupled to the second connection structure.

A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.

According to one embodiment of the present disclosure, there is provided a substrate processing method including: providing a substrate; forming a seed layer on a surface of the substrate by heating a stage on which the substrate is placed to a first temperature and supplying a first source gas to the substrate; and forming a metal-containing film by heating the stage on which the substrate is placed to a second temperature and supplying a second source gas and a first reducing gas to the substrate on which the seed layer is formed.

It is a two-dimensional semiconductor-metal ohmic-contact structure, a preparation method therefor and use thereof, wherein the ohmic-contact structure comprises two-dimensional semiconductor having semimetal antimony or an alloy containing semimetal antimony deposited thereon to form an ideal van der Waals interface with strong orbital hybridization, and semimetal antimony is deposited on the two-dimensional semiconductor by high-vacuum evaporation; which is applied to semiconductor devices and realizes ultralow contact resistance between the metal and the two-dimensional semiconductor and significantly improve the performance of two-dimensional semiconductor devices.

In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.