A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability.

There is provided a semiconductor device including: a lead frame including a first opening portion; a resin filled in the first opening portion; and a semiconductor element electrically connected to the lead frame, wherein a side wall surface of the lead frame in the first opening portion has a larger average surface roughness than an upper surface of the lead frame.

The present invention relates to a method of connecting circuit elements and a corresponding system for connecting circuit elements. The method includes providing a plurality of flexible circuit elements on a carrier element; forming a connecting structure. The formed connecting structure includes at least two contact points; and operative connections between each of the plurality of flexible circuit elements and the at least two contact points. The method further includes severing the operative connection between at least one of the plurality of flexible circuit elements and the at least two contact points.

In some aspects, the disclosure is directed a module for improving mechanical, electrical, or thermal performance. In some embodiments, the module includes a bottom surface, a side surface, a first solder bump disposed on the bottom surface, and a second solder bump disposed on the bottom surface. In some embodiments, the bottom surface extends in a first lateral direction and a second lateral direction perpendicular to the first lateral direction. In some embodiments, the side surface extends in a vertical direction perpendicular to the first lateral direction and the second lateral direction. In some embodiments, the second solder bump is adjacent to the side surface. In some embodiments, the first solder bump has a first length in the first lateral direction. In some embodiments, the second solder bump has a second length in the first lateral direction. In some embodiments, the first length is greater than the second length.

In the present invention, in order to reduce parasitic inductances of a gate line and a source line of a power module to reduce a current deviation (current balancing) which is a problem when the power module composed of a plurality of parallel chips is driven, in a power module including a plurality of power semiconductor chips connected to gate lines and source lines extending from gate pins and source pins in parallel by different distances, a current area of each of the gate lines and the source lines connected to chips other than a first chip closest to the gate pin and the source pin is formed larger than a current area of each of the gate line and the source line connected to the first chip.

A semiconductor device is a substrate inserted lead-type semiconductor device to be mounted through insertion of a plurality of lead terminals into a plurality of respective through holes of a substrate. The semiconductor device includes: an energization controller including a semiconductor element and wiring; a sealing resin to cover the energization controller; and the lead terminals each having one end side connected to the energization controller and the other end side protruding from the sealing resin. The lead terminals each have a protrusion formed on a part of the other end side protruding from the sealing resin.

According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.

A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.

A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 μm or more, diameters of 10 μm or below, and inter-pillar spacing below 20 μm. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.