A hybrid embedded packaging structure and a manufacturing method thereof are disclosed. The structure includes: a substrate with a first insulating layer, a conductive copper column, a chip-embedded cavity and a first circuit layer; a first electronic device arranged inside the chip-embedded cavity; a second electronic device arranged on a back surface of the first electronic device; a second insulating layer covering and filling the chip-embedded cavity and an upper layer of the substrate, exposing part of the first circuit layer and a back surface of part of the second electronic device or part of the first electronic device; a second circuit layer electrically connected with the conductive copper column and a terminal of the first electronic device; a conducting wire electrically connecting the first circuit layer with a terminal of the second electronic device; and a protection cover arranged on the top surface of the substrate.

Provided is a photosensitive resin composition containing: a photopolymerizable compound (A) having an ethylenically unsaturated group; a photopolymerization initiator (B); and an inorganic filler (F), in which the photopolymerizable compound (A) having an ethylenically unsaturated group includes a photopolymerizable compound (A1) having an acidic substituent and an alicyclic structure together with an ethylenically unsaturated group, and the inorganic filler (F) includes an inorganic filler surface-treated with a coupling agent without at least one functional group selected from the group consisting of an amino group and a (meth)acryloyl group. The present disclosure also provides a photosensitive resin composition for photo via formation, and a photosensitive resin composition for interlayer insulating layer. The present disclosure further provides: a photosensitive resin film and a photosensitive resin film for interlayer insulating layer, each of which contains the photosensitive resin composition; a multilayered printed wiring board and a semiconductor package; and a method for producing a multilayered printed wiring board.

A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. A plurality of conductive balls is placed over a circuit substrate, where each of the conductive balls is placed over a contact area of one of a plurality of contact pads that is accessibly revealed by a patterned mask layer. The conductive balls are reflowed to form a plurality of external terminals with varying heights connected to the contact pads of the circuit substrate, where a first external terminal of the external terminals formed in a first region of the circuit substrate and a second external terminal of the external terminals formed in a second region of the circuit substrate are non-coplanar.

An electronic device is disclosed and includes a conductive layer, a first dielectric layer, and a second dielectric layer, in which the second dielectric layer is disposed on the first dielectric layer, the conductive layer is disposed between the first dielectric layer and the second dielectric layer, the first dielectric layer has a first transmittance for a light, the second dielectric layer has a second transmittance for the light, and the first transmittance is different from the second transmittance.

An electronic carrier and a method of manufacturing an electronic carrier are provided. The electronic carrier includes a first interconnection structure and a second interconnection structure. The first interconnection structure includes a first patterned conductive layer having a first pattern density. The second interconnection structure is laminated to the first interconnection structure and includes a second patterned conductive layer having a second pattern density higher than the first pattern density. The first interconnection structure is electrically coupled to the second interconnection structure through a first non-soldering joint between and outside of the first interconnection structure and the second interconnection structure.

A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.

Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.

A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

The present invention provides a prepreg for a coreless substrate and a coreless substrate and a semiconductor package using the prepreg, which can satisfy heat resistance, low thermal expansion, and bonding strength with a metal circuit at a level required for the coreless substrate. Specifically, the prepreg for a coreless substrate contains a thermosetting resin composition containing (a) dicyandiamide, (b) an adduct of a tertiary phosphine and quinones, (c) an amine compound having at least two primary amino groups, and (d) a maleimide compound having at least two primary amino groups having at least two N-substituted maleimide groups. Instead of (c) the amine compound having at least two primary amino groups and (d) the maleimide compound, having at least two N-substituted maleimide groups, (X) an amino-modified polyimide resin obtained by reacting them may be used.