A semiconductor device manufacturing method includes a molding step including disposing a control pin between an inlet and a control wire and on a line connecting the inlet and the control wire in a plan view of the semiconductor device, injecting molding resin raw material into a cavity through the inlet, filling the cavity with the molding resin raw material, and sealing a semiconductor chip and a control element disposed on a main current lead frame and a control lead frame. In this way, the flow velocity of the molding resin raw material flowing to the control wire is reduced.

A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.

A molding device for producing a molded module. The molding device has one tool part and one further tool part, which together enclose a cavity. At least one of the tool parts has at least one dividing web arranged and configured to subdivide the cavity into at least a low-pressure sub-cavity and a high-pressure sub-cavity. The tool part has at least two feed channels, of which a low-pressure feed channel opens into the low-pressure sub-cavity and has a smaller cross-section at least over a longitudinal portion than a high-pressure feed channel opening into the high-pressure sub-cavity. The low-pressure feed channel is configured to become pressure-resistantly blocked through hardening of the molding compound once a predetermined time interval has elapsed or during the interval. The high-pressure feed channel is configured to conduct a molding pressure into the cavity for a longer time interval than the low-pressure feed channel.

An electronic component comprising a plastic package and an electric chip which is inside the package. The electronic component comprises a metallic die pad and a metallic first support structure extends from the die pad to a first support point on one of the side surfaces of the plastic package. The electronic component also comprises a metallic opposing pad and a metallic second support structure which extends from the opposing pad to a second support point on one of the side surfaces of the plastic package.

A package structure includes first/second/third package components, a thermal interface material (TIM) structure overlying the first package component opposite to the second package component, and a heat dissipating component disposed on the third package component and thermally coupled to the first package component through the TIM structure. The first package component includes semiconductor dies and an insulating encapsulation encapsulating the semiconductor dies, the second package component is interposed between the first and third package components, and the semiconductor dies are electrically coupled to the third package component via the second package component. The TIM structure includes a dielectric dam and thermally conductive members including a conductive material, disposed within areas confined by the dielectric dam, and overlying the semiconductor dies. A manufacturing method of a package structure is also provided.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate that includes a plurality of vias, a first chip stack on the substrate and including a plurality of first semiconductor chips that are sequentially stacked on the substrate, and a plurality of first non-conductive layers between the substrate and the first chip stack and between neighboring first semiconductor chips. Each of the first non-conductive layers includes first extensions that protrude outwardly from first lateral surfaces of the first semiconductor chips. The more remote the first non-conductive layers are from the substrate, the first extensions protrude a shorter length from the first lateral surfaces of the first semiconductor chips.

Thermosetting resin compositions useful for liquid compression molding encapsulation of a reconfigured wafer are provided. The so-encapsulated molded wafer offers improved resistance to warpage, compared to reconfigured wafers encapsulated with known encapsulation materials.

An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.

A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.