An integrated circuit (IC) substrate manufacturing process provides time-dependent device characteristic variation due to hydrogen absorption by including one or more gettering layers near the devices that would otherwise absorb hydrogen and exhibit the variation as the hydrogen migrates in the devices. The method includes forming or mounting the devices on a top surface of the semiconductor wafer in die areas of the substrate, forming semiconductor structures in the semiconductor die areas, forming a getter layer above or adjacent to the devices in the die areas, and processing the wafer with one or more processes exposing the wafer to vapor having a hydrogen content, whereby an amount of hydrogen absorbed by the devices is reduced by presence of the getter layer. The method produces wafers including semiconductor dies with reduced hydrogen absorption by the devices and packaged ICs including the dies.

Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

The present disclosure is directed to at least one embodiment of a die including a sidewall having a uniform surface and an irregular surface. The uniform surface may be a scalloped surface and scallops of the scalloped surface are substantially the same size and shape relative to each other. The irregular surface has a more irregular texture as compared to the uniform surface. The irregular surface may include a plurality of randomly spaced high points and a plurality of randomly spaced low points that are between adjacent ones of the high points. In a method of manufacturing the die, a cavity is pre-formed in a substrate and a multilayer structure is formed on the substrate. The multilayer structure includes an active area that is aligned with and overlies the cavity. After the multilayer structure is formed, at least one recess is formed extending into the multilayer structure to the cavity. Forming the recess forms a die structure suspended above the cavity and an extension extending from the die structure to a suspension structure surrounding the die structure. The die structure is released from the die suspension structure by breaking the extension.

A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

A method and an electronic device that includes an isolation structure having a dielectric material on or in a semiconductor surface layer, and a passive circuit component having a metal silicide structure on a side of the isolation structure, there the metal silicide structure includes a metal silicide portion and a dielectric portion, the dielectric portion of the metal silicide structure including one of silicon nitride, silicon oxide, silicon carbide, silicon carbon nitride, and silicon oxynitride. The method includes forming a dielectric material of the isolation structure on or in the semiconductor surface layer, forming a silicon-rich dielectric layer on a side of the isolation structure, and siliciding the silicon-rich dielectric layer to form the metal silicide structure on the side of the isolation structure.

A semiconductor device includes a capacitor and a resistor. The capacitor includes a first plate, a capacitor dielectric layer disposed over the first plate, and a second plate disposed over the capacitor dielectric layer. The resistor includes a thin film. The thin film of the resistor and the first plate of the capacitor, formed of a same conductive material, are defined in a single patterning process.

A semiconductor device includes a capacitor and a resistor. The capacitor includes a first plate, a capacitor dielectric layer disposed over the first plate, and a second plate disposed over the capacitor dielectric layer. The resistor includes a thin film. The thin film of the resistor and the first plate of the capacitor, formed of a same conductive material, are defined in a single patterning process.

A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.

The present disclosure provides a substrate integrated with a passive device and a method for manufacturing the same, and belongs to the technical field of communications. The substrate integrated with a passive device according to the present disclosure includes a dielectric layer provided with a first connection via; and the passive device at least including an inductor. The inductor includes a plurality of first sub-structures and a plurality of second sub-structures respectively disposed on two opposite sides of the dielectric layer, and two adjacent first sub-structures of the plurality of first sub-structures are short-circuited by a corresponding one of the plurality of second sub-structures through the first connection via penetrating through the dielectric layer, so as to form an induction coil of the inductor.