A method for fabricating semiconductor devices is disclosed. The method includes forming a recess along a top surface of a semiconductor substrate. The method includes forming a nitride-based spacer layer extending along a first sidewall of the recess. The method includes forming a field oxide layer in the recess extending along a bottom surface of the recess, while a lateral tip of the field oxide layer is blocked from extending into any portion of the semiconductor substrate other than the recess by the nitride-based spacer layer.

A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.

Provided are a shallow trench isolation structure and a method for manufacturing the same. The shallow trench isolation structure includes a substrate, a first isolation structure, a second isolation structure and a third isolation structure. The substrate includes a first trench. The first isolation layer is located in the first trench and provided with a second trench. The second isolation layer is located in the second trench and provided with a third trench. The third isolation layer fills the third trench. The second trench is a V-shaped trench, and a bottom surface of the second isolation layer is a V-shaped surface that is adapted to a shape of the second trench.

A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

A semiconductor device includes: a metal-oxide semiconductor (MOS) transistor on a substrate; a deep trench isolation structure in the substrate and around the MOS transistor; and a trap rich isolation structure in the substrate and surrounding the deep trench isolation structure. Preferably, the deep trench isolation structure includes a liner in the substrate and an insulating layer on the liner, in which the top surfaces of the liner and the insulating layer are coplanar. The trap rich isolation structure is made of undoped polysilicon and the trap rich isolation structure includes a ring surrounding the deep trench isolation structure according to a top view.

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure which has a first corner. The semiconductor device also includes a first well region with a first conductive type. The semiconductor device includes further includes a gate structure over the first well region and covers a portion of the first corner of the first isolation structure. In addition, the semiconductor device includes a first doped region and a second doped region disposed on two opposites of the gate structure. Each of the first doped region and the second doped region has the first conductive type. The semiconductor device also includes a first counter-doped region in the first well region with a second conductive type different from the first conductive type. The first counter-doped region covers the first corner of the first isolation structure.

According to one or more embodiments, a method for manufacturing a semiconductor device comprises forming a stacked film that comprises alternating first insulating layers and second insulating layers. A first insulating film, an electric charge storage layer, a second insulating film, and a first semiconductor layer are then formed in a hole in the stacked film. The method further includes forming a first recess in the stacked film, then supplying a first gas and a deuterium gas to the first recess. The first gas comprises hydrogen and oxygen.

A semiconductor device structure comprises a region of semiconductor material comprising a first conductivity type, a first major surface, and a second major surface opposite to the first major surface. A first trench gate structure includes a first trench extending from the first major surface into the region of semiconductor material, a first dielectric structure is over sidewall surfaces and a portion of a lower surface of the first trench, wherein the first dielectric structure comprises a first opening adjacent to the lower surface of the first trench, a first recessed contact extends through the first opening, and a first contact region is over the first recessed contact within the first trench, wherein the first recessed contact and the first contact region comprise different materials. A first doped region comprising a second dopant conductivity type opposite to the first conductivity type is in the region of semiconductor material and is spaced apart from the first major surface and below the first trench. A gate contact region is in the region of semiconductor material and is electrically connected to the first doped region.

Semiconductor devices and methods of forming the same include forming a buried power rail in a substrate, having a first dielectric liner of a first thickness separating the buried power rail from the substrate. An isolation structure is formed over the buried power rail, having a second dielectric liner of a second thickness, greater than the first thickness, separating the isolation structure from the substrate. A first transistor device is formed on the substrate. The first transistor device has a first width. A second transistor device is formed above the first transistor device, and has a second width smaller than the first width. A conductive contact is formed to the buried power rail.

A method of filling cavities in a semiconductor structure during fabrication. A layer of a first material, e.g., a polysilazane, is deposited on the semiconductor, and subjected to a first thermal process to change its chemical composition, e.g., to change it to silicon dioxide. It is then etched back, and the cycle of deposition, and thermal processing is repeated. The etch-back may also be repeated in one or more of the cycles after the first cycle, and a second thermal process, that may increase the density of one or more of the deposited layers, may be performed in one or more of the cycles.