A method of forming a semiconductor device includes providing a substrate having a patterned film including manganese; depositing a graphene layer over exposed surfaces of the patterned film; depositing a dielectric layer containing silicon and oxygen over the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

The present application discloses a method for fabricating a semiconductor device. The method includes: providing a substrate including a plurality of first regions and second regions; forming a plurality of bit line contacts over the first regions of the substrate; forming a plurality of bit lines respectively over the plurality of bit line contacts; forming a plurality of capacitor contacts respectively over the second regions of the substrate; forming a plurality of capacitor plugs respectively over the plurality of capacitor contacts; forming a plurality of first spacers respectively over a plurality of protruding portions of the plurality of capacitor plugs, wherein a width of the first spacer is larger than a width of the capacitor plug; and forming a plurality of capacitor structures over the plurality of first spacers; wherein at least one of the plurality of bit lines is an undulating stripe extending between two adjacent capacitor contacts.

A method includes forming one or more vias in a first layer, forming one or more vias in at least a second layer different than the first layer, aligning at least a first via in the first layer with at least a second via in the second layer, and bonding the first layer to the second layer by filling the first via and the second via with solder material using injection molded soldering.

An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

A semiconductor device includes a substrate having an active region, a first insulating layer on the substrate, a second insulating layer on the first insulating layer, an etch stop layer between the first insulating layer and the second insulating layer, a via contact in the first insulating layer and electrically connected to the active region, an interconnection electrode in the second insulating layer and electrically connected to the via contact, a conductive barrier layer on a side surface and a lower surface of the interconnection electrode and having an extension portion extending to a partial region of a side surface of the via contact, and a side insulating layer on a side region of the via contact below the extension portion of the conductive barrier layer, the side insulating layer including the same material as a material of the etch stop layer.

The present disclosure relates to a semiconductor device with an air gap below a landing pad and a method for forming the semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.