A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.

A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings.

A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a bottom and sidewalls of the opening with a first substrate bias; forming a second barrier layer on the first barrier layer with a second substrate bias, the second substrate bias being greater than the first substrate bias, the first and second barrier layers forming collectively a barrier layer; removing a portion of the barrier layer on the bottom and on the sidewalls of the opening by bombarding the barrier layer with a plasma with a vertical substrate bias; and forming a second metal layer filling the opening.

A manufacturing method of a package structure of an electronic device, including the following steps, is provided. A first seed layer is formed on a carrier plate. A first metal layer is formed on the first seed layer. A first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. A first plasma treatment is performed on the first insulating layer and the exposed portion of the first metal layer. After performing the first plasma treatment, the carrier plate formed with the first seed layer, the first metal layer, and the first insulating layer is placed in a microenvironment controlling box. After taking the carrier plate out of the microenvironment controlling box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer.

A method of electroplating metal into features of a partially fabricated electronic device on a substrate having high open area portions is provided. The method includes initiating a bulk electrofill phase with a pulse at a high level of current; reducing the current to a baseline current level; and optionally increasing the current in one or more steps until electroplating is complete.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate having a connection hole thereon, annular protrusions and annular grooves alternately arranged along a direction parallel to a center line of the connection hole being provided on a hole wall of the connection hole; filling a barrier block in each of the annular grooves; removing the annular protrusions along a direction perpendicular to the hole wall of the connection hole; removing the barrier blocks; and forming a connection layer in the connection hole. After the annular protrusions are removed, roughness of the hole wall of the connection hole is reduced, such that a conductive seed layer is prevented from being broken, thereby avoiding generation of voids in the connection layer, and improving performance of the semiconductor structure.

In one example, an electroplating system comprises a first bath reservoir, a second bath reservoir, a clamp, a first anode in the first bath reservoir, a second anode in the second bath reservoir, and a direct current power supply. The first bath reservoir contains a first electrolyte solution that includes an alkaline copper-complexed solution. The second bath reservoir contains a second electrolyte solution that includes an acidic copper plating solution. The direct current power supply generates a first direct current between the clamp and the first anode to electroplate a first copper layer on the cobalt layer of the wafer submerged in the first electrolyte solution. The direct current power supply then generates a second direct current between the clamp and the second anode to electroplate a second copper layer on the first copper layer of the wafer submerged in the second electrolyte solution.

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

An electroplating apparatus for electroplating metal on a substrate includes a plating chamber configured to contain an electrolyte, a substrate holder configured to hold and rotate the substrate during electroplating, an anode, and an azimuthally asymmetric auxiliary electrode configured to be biased both anodically and cathodically during electroplating. The azimuthally asymmetric auxiliary electrode (which may be, for example, C-shaped), can be used for controlling azimuthal uniformity of metal electrodeposition by donating and diverting ionic current at a selected azimuthal position. In another aspect, an electroplating apparatus for electroplating metal includes a plating chamber configured to contain an electrolyte, a substrate holder configured to hold and rotate the substrate during electroplating, an anode, a shield configured to shield current at the periphery of the substrate; and an azimuthally asymmetric auxiliary anode configured to donate current to the shielded periphery of the substrate at a selected azimuthal position on the substrate.