A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

A bonding structure formed on a substrate includes an indium layer and a passivating nickel plating formed on the indium layer. The nickel plating serves to prevent a reaction involving the indium layer.

An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

A method for fabricating a semiconductor device includes forming a mold structure on a substrate, the mold structure including inter-electrode insulating films and sacrificial films alternately and repeatedly stacked in a first direction, forming a channel hole which penetrates the mold structure in the first direction, forming a vertical channel structure inside the channel hole, removing the sacrificial films to form trenches which expose the vertical channel structure, the trenches extending in a second direction perpendicular to the first direction, and forming metallic lines which fill the trenches, respectively, each of the metallic lines being formed as a single layer, using a wet deposition process.

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

Exemplary methods of plating are described. The methods may include contacting a patterned substrate with a plating bath in a plating chamber. The patterned substrate includes at least one metal interconnect with a contact surface that is exposed to the plating bath. The metal interconnect is made of a first metal characterized by a first reduction potential. The methods further include plating a diffusion layer on the contact surface of the metal interconnect. The diffusion layer is made of a second metal characterized by a second reduction potential that is larger than the first reduction potential of the first metal in the metal interconnects. The plating bath also includes one or more ions of the second metal and a grain refining compound that reduces the formation of pinhole defects in the diffusion layer.

A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.

Various embodiments relate to methods, apparatus, and systems for forming an interconnect structure, or a portion thereof. The method may include contacting the substrate with a functionalization bath comprising a first solvent and a functionalization reactant to form a modified first material, and then depositing a second material on the modified first material through electroless plating, electroplating, chemical vapor deposition, or atomic layer deposition. The first material may be a dielectric material, a barrier layer, or a liner, and the second material may be a barrier layer or a barrier layer precursor, a liner, a seed layer, or a conductive metal that forms the interconnect of the interconnect structure, according to various embodiments.

There is provided a method for manufacturing a flexible electrode, the method comprising: cleaning a plastic substrate; forming a metal-oxide seed layer on the plastic substrate by sputtering a metal oxide on the plastic substrate; and forming a metal plating layer on the metal oxide seed layer using an electroless plating.