Embodiments of the present invention provide a method for manufacturing a semiconductor structure, which includes: a base is provided and a stack layer is formed on the base, wherein the stack layer includes at least a first sacrificial layer, and a material of the first sacrificial layer includes an amorphous elemental semiconductor material; second hard mask patterns are formed on the first sacrificial layer through a self-aligned process; a doping process is performed, which includes the operation that a region of the first sacrificial layer exposed from gaps between the second hard mask patterns is doped; the second hard mask patterns are removed; and an undoped region of the first sacrificial layer is removed through a selective etching process so as to form first sacrificial patterns.

The present disclosure provides a method for preparing a semiconductor device with air spacer for decreasing electrical coupling. The method comprises: forming a plurality of composite pillars over a substrate, wherein the composite pillars include conductive pillars and dielectric caps over the conductive pillars; transforming a sidewall portion of the conductive pillar into a first transformed portion; removing the first transformed portion such that a width of the dielectric cap is greater than a width of a remaining portion of the conductive pillar; forming a supporting pillar between adjacent two of the plurality of composite pillars; and forming a sealing layer at least contacts a top portion of the supporting pillar and a top of the dielectric cap, and air spacers are formed between the sealing layer, the supporting pillar and the remaining portions of the conductive pillars.

In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.

Semiconductor devices and methods of forming conductive lines in the same include forming a cut region in a first dielectric layer, the cut region having a first width. A second dielectric plug is formed in the cut region. A mask is formed, over the first dielectric layer, that defines at least one trench region that crosses the second dielectric plug, with the at least one trench region having a second width that is smaller than the first width. Material from the first dielectric layer in the trench regions is etched away, using a selective anisotropic etch that leaves the second dielectric plug in place, to form trenches in the first dielectric layer. Conductive material is deposited in the trenches to form conductive lines that are separated by the second dielectric plug.

Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate including a plurality of active areas and first isolation structures arranged at intervals along a first direction; gate structures located in the active areas and the first isolation structures. Top surfaces of the active areas extend beyond top surfaces of the gate structures; second isolation structures with a preset height located on surfaces of the gate structures, and the top surfaces of the second isolation structures are flush with the top surfaces of the active areas.

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

An exemplary semiconductor structure includes a substrate defining a first trench; a first refractory metal liner coating the first trench; a heavy metal liner coating the first refractory metal liner; a copper structure filling the first trench over the heavy metal liner; a generally planar capping dielectric layer on top of the substrate and the copper structure; a low-k dielectric layer on top of the capping dielectric layer, wherein the low-k dielectric layer defines a second trench; a second refractory metal liner coating the second trench; a metal line filling the second refractory metal liner; and a metal via protruding from the metal line.

A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.

Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.