Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

A processing method for processing a single-crystal silicon wafer that has a first surface and a second surface formed in such a manner that a specific crystal plane included in a crystal plane {100} is exposed in each of the first and second surfaces and has devices formed in the respective regions marked out by planned dividing lines in the first surface. The method includes forming dividing origins along each planned dividing line, forming a separation layer along the crystal plane of the second surface through relatively moving a focal point and the wafer along a first direction that is parallel to the crystal plane of the second surface and in which an acute angle formed between the first direction and the crystal orientation <100> is equal to or smaller than 5°, and separating the wafer into a first-surface-side wafer including devices and a second-surface-side wafer including no devices.

A processing method for processing a single-crystal silicon wafer that has a first surface and a second surface formed in such a manner that a specific crystal plane included in a crystal plane {100} is exposed in each of the first and second surfaces and has devices formed in the respective regions marked out by planned dividing lines in the first surface. The method includes forming dividing origins along each planned dividing line, forming a separation layer along the crystal plane of the second surface through relatively moving a focal point and the wafer along a first direction that is parallel to the crystal plane of the second surface and in which an acute angle formed between the first direction and the crystal orientation <100> is equal to or smaller than 5°, and separating the wafer into a first-surface-side wafer including devices and a second-surface-side wafer including no devices.

Disclosed herein is a packaged wafer manufacturing method including the steps of forming a groove along each division line on the front side of a wafer, each groove having a depth greater than the finished thickness of the wafer, next removing a chamfered portion from the outer circumference of the wafer to thereby form a step portion having a depth greater than the depth of each groove, next setting a die of a molding apparatus on the bottom surface of the step portion of the wafer in the condition where a space is defined between the die and the wafer, and next filling a mold resin into this space. Accordingly, the device area of the wafer is covered with the mold resin and each groove of the wafer is filled with the mold resin to thereby obtain a packaged wafer.

A wafer dividing method includes forming modified layers which will be starting points of division, integrally attaching an annular frame and the wafer together through a dicing tape, directing the wafer downward and expanding the dicing tape to divide, into individual device chips, the wafer along the modified layers formed along the streets, counting particles scattered at the time of division of the wafer by a particle counter disposed in a dust collection path set directly below the wafer, and determining, on the basis of the number of the particles, whether or not the modified layers have been properly formed, at the time of carrying out the dividing step.

A wafer dividing method includes forming modified layers which will be starting points of division, integrally attaching an annular frame and the wafer together through a dicing tape, directing the wafer downward and expanding the dicing tape to divide, into individual device chips, the wafer along the modified layers formed along the streets, counting particles scattered at the time of division of the wafer by a particle counter disposed in a dust collection path set directly below the wafer, and determining, on the basis of the number of the particles, whether or not the modified layers have been properly formed, at the time of carrying out the dividing step.

A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.

A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.