Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

To more reliably suppress deterioration in characteristics due to signals (distortions) other than input and output waves while suppressing manufacturing cost. A semiconductor device according to the present disclosure includes a circuit substrate including an insulating film layer located above a predetermined semiconductor substrate and a semiconductor layer located above the insulating film layer, a plurality of passive elements provided on the circuit substrate and electrically connected with one another, and an electromagnetic shield layer locally provided in the insulating film layer corresponding to a portion where at least one of the plurality of passive elements is provided, and the electromagnetic shield layer and the semiconductor substrate are electrically separated from each other.

To more reliably suppress deterioration in characteristics due to signals (distortions) other than input and output waves while suppressing manufacturing cost. A semiconductor device according to the present disclosure includes a circuit substrate including an insulating film layer located above a predetermined semiconductor substrate and a semiconductor layer located above the insulating film layer, a plurality of passive elements provided on the circuit substrate and electrically connected with one another, and an electromagnetic shield layer locally provided in the insulating film layer corresponding to a portion where at least one of the plurality of passive elements is provided, and the electromagnetic shield layer and the semiconductor substrate are electrically separated from each other.

To more reliably suppress deterioration in characteristics due to signals (distortions) other than input and output waves while suppressing manufacturing cost. A semiconductor device according to the present disclosure includes a circuit substrate including an insulating film layer located above a predetermined semiconductor substrate and a semiconductor layer located above the insulating film layer, a plurality of passive elements provided on the circuit substrate and electrically connected with one another, and an electromagnetic shield layer locally provided in the insulating film layer corresponding to a portion where at least one of the plurality of passive elements is provided, and the electromagnetic shield layer and the semiconductor substrate are electrically separated from each other.

To more reliably suppress deterioration in characteristics due to signals (distortions) other than input and output waves while suppressing manufacturing cost. A semiconductor device according to the present disclosure includes a circuit substrate including an insulating film layer located above a predetermined semiconductor substrate and a semiconductor layer located above the insulating film layer, a plurality of passive elements provided on the circuit substrate and electrically connected with one another, and an electromagnetic shield layer locally provided in the insulating film layer corresponding to a portion where at least one of the plurality of passive elements is provided, and the electromagnetic shield layer and the semiconductor substrate are electrically separated from each other.

The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

A new architecture to fabricate high-rise fully monolithic three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all known prior arts in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAS in a monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.