A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

A semiconductor device (1) according to the present disclosure includes: an n-channel depletion-mode transistor (10); an input matching circuit inside which the gate terminal (11) and the ground terminal (22) are DC-connected; a self-bias circuit (26) including a resistor (14) biasing the transistor (10) by a voltage drop due to a current flowing through the resistor (14), and a capacitor (15) connected in parallel to the resistor 14) and regarded as short-circuit at a frequency of the high-frequency power; and a diode (31) having an endmost anode connected to the source terminal (12) and an endmost cathode connected to the ground terminal (22), and connected in one stage or connected in series in a plurality of stages in the same direction.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.

A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.

The present application provides a method for manufacturing a semiconductor structure and a semiconductor structure, relating to the field of semiconductor technology. The method for manufacturing a semiconductor structure includes: providing a substrate; forming a metal wiring layer on the substrate, a surface of the metal wiring layer having positive charges; and providing a reaction gas to the metal wiring layer.

The present disclosure relates to a semiconductor device and a forming method thereof. The forming method includes: providing a substrate; forming node contacts inside the substrate; forming landing pads on an upper surface of the substrate, where the landing pad is in contact with the node contact; forming a barrier layer on exposed surfaces of the landing pads and the node contacts; and after performing an electrical test on the semiconductor device on which the barrier layer is formed, removing the barrier layer on an upper surface of the landing pads.

The present disclosure provides a method for manufacturing a memory, including: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer, and forming a plurality of discrete pseudo bit line layers on the substrate; forming a support layer, the support layer filling areas between the adjacent pseudo bit line layers; removing the pseudo bit line layers to form bit line spaces between adjacent parts of the support layer; forming bit line structures, the bit line structures filling the bit line spaces, and the bit line structures including a bit line conductive layer and a bit line insulating layer sequentially stacked; and removing the support layer, and forming openings between the adjacent bit line structures.

A novel image processing method is provided. In a display device in which a video signal is individually supplied to a screen divided into two, the entire screen is subjected to up-conversion processing after being divided, and another up-conversion processing is performed for a boundary portion of the screen divided into two. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion are performed in parallel with the use of a plurality of arithmetic units. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion can be performed using different algorithms.