The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP.

The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP.

Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.

Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.

In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.

A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.