Patent classifications
H01L2224/13011
Conductive member cavities
In some examples, a quad flat no lead (QFN) semiconductor package comprises a flip chip semiconductor die having a surface and circuitry formed in the surface; and a conductive pillar coupled to the semiconductor die surface. The conductive pillar has a distal end relative to the semiconductor die, the distal end having a cavity including a cavity floor and one or more cavity walls circumscribing the cavity floor. The one or more cavity walls are configured to contain solder.
Wiring board
A wiring board includes: an insulating layer; and a connection terminal formed on the insulating layer. The connection terminal includes a first metal layer laminated on the insulating layer, a second metal layer laminated on the first metal layer, a metal pad laminated on the second metal layer, and a surface treatment layer that covers an upper surface and a side surface of the pad and that is in contact with the upper surface of the insulating layer. An end portion of the second metal layer is in contact with the surface treatment layer, and an end portion of the first metal layer is positioned closer to a center side of the pad than the end portion of the second metal layer is to form a gap between the end portion of the first metal layer and the surface treatment layer.
SUBSTRATE PAD AND DIE PILLAR DESIGN MODIFICATIONS TO ENABLE EXTREME FINE PITCH FLIP CHIP (FC) JOINTS
An electronic component includes a device die and a substrate. The device die includes conductive contacts with conductive pillars conductively affixed to conductive contact. The conductive pillars include a cavity formed in an end of the conductive pillar opposite the conductive contact. The substrate includes of conductive pads that are each associated with one of the conductive contacts. The conductive pads include a conductive pad conductively affixed to the substrate, and a conductive ring situated within a cavity in the end conductive rings have a capillary formed along an axis of the conductive ring. A solder material fills the capillary of each of the conductive rings and the cavity formed in the end of the associated conductive pillars to form a conductive joint between the pillars and the conductive pads.
Eutectic Electrode Structure of Flip-chip LED Chip and Flip-chip LED Chip
A light emitting diode includes: a light emitting layer arranged on at least part of a first semiconductor layer, and a second semiconductor layer; a local defect region over a portion of the second semiconductor layer and extending downward to the first semiconductor layer; a metal layer over a portion of the second semiconductor layer; an insulating layer covering the metal layer, the second and first semiconductor layers in the local defect region, with opening structures over the local defect region and the metal layer, respectively; and an electrode structure over the insulating layer and having a first layer and a second layer, and including a first-type electrode region and a second-type electrode region; wherein an upper surface and a lower surface of the first layer are not flat, and a lower surface of the second layer are both flat.
Semiconductor chip suitable for 2.5D and 3D packaging integration and methods of forming the same
The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.
TERMINAL AND CONNECTION METHOD
An object of the present technology is to prevent damage in a bonded portion between a semiconductor chip and a substrate in a semiconductor device in which the semiconductor chip is mounted on the substrate.
A terminal is disposed between an electrode of an element and an electrode of a substrate on which the element is mounted, and electrically connects the electrode of the element and the electrode of the substrate. The terminal includes a plurality of unit lattices and a coupling portion. The unit lattices included in the terminal are formed by bonding a plurality of beams in a cube shape. The coupling portion included in the terminal couples adjacent unit lattices among the plurality of unit lattices.
SUPPORTING BACKPLANE, MANUFACTURING METHOD THEREFOR AND BACKPLANE
The present disclosure provides a supporting substrate, including: a base substrate and a plurality of connecting electrodes provided on the base substrate, wherein a clamping electrode is provided on a side of at least one of the connecting electrodes facing away the base substrate, the clamping electrode is electrically connected with a corresponding connecting electrode and configured to be capable of clamping and fixing an electrode pin of the micro-light emitting device. The present disclosure also provides a manufacturing method for the supporting substrate, and a backplane.
Semiconductor device and semiconductor device manufacturing method
A semiconductor device including a terminal that is formed using copper, that is electrically connected to a circuit element, and that includes a formation face formed with a silver-tin solder bump such that a nickel layer is interposed between the terminal and the solder bump, wherein the nickel layer is formed on a region corresponding to part of the formation face.
Bump structure having a side recess and semiconductor structure including the same
The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.
Interconnect using nanoporous metal locking structures
Embodiments relate to the design of a device capable of maintaining the alignment an interconnect by resisting lateral forces acting on surfaces of the interconnect. The device comprises a first body comprising a first surface with a nanoporous metal structure protruding from the first surface. The device further comprises a second body comprising a second surface with a locking structure to resist a lateral force between the first body and the second body during or after assembly of the first body and the second body.