Patent classifications
H01L2224/13021
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A semiconductor package includes a package substrate, a semiconductor chip, connection pins and a molding member. The package substrate includes wiring patterns provided respectively in insulation layers, and has insertion holes extending from an upper surface of the package substrate in a thickness direction that expose portions of the wiring patterns in different insulation layers. The semiconductor chip is disposed on the package substrate, and has a first surface on which chip pads are formed. The connection pins are provided on the chip pads, respectively, and extend through corresponding ones of the insertion holes and electrically connect to the portions of the wiring patterns, respectively, that are exposed by the insertion holes. The molding member is provided on the package substrate to cover the semiconductor chip.
Semiconductor device and method of forming micro interconnect structures
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
DISPLAY DEVICE AND TILED DISPLAY DEVICE
A display device including a substrate having a first side surface, a first surface, a second surface opposite to the first surface, a first chamfered surface extending from an edge of the first surface to the first side surface, a second chamfered surface extending from an edge of the second surface t the first side surface, a pixel on the first surface of the substrate and including a light emitting element configured to emit light, a first driving pad at the edge of the first surface of the substrate and electrically connected to the pixel, and a side wiring on the first surface, the first chamfered surface, the first side surface, the second chamfered surface, and the second surface of the substrate. The first driving pad has a flat portion connected to the side wiring.
DISPLAY DEVICE AND TILED DISPLAY DEVICE INCLUDING THE SAME
A display device includes a substrate including a first surface, a second surface opposite to the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and a side surface connecting the first chamfered surface to the second chamfered surface, a pixel on the first surface of the substrate and including a light emitting element to emit light, a plurality of front pad parts on an edge of the first surface of the substrate and electrically connected to the pixel, a plurality of rear pad parts on an edge of the second surface of the substrate, and a plurality of side surface connection lines on the side surface of the substrate electrically connecting the plurality of front pad parts to the plurality of rear pad parts.
BONDING ELEMENT AND METHOD FOR MANUFACTURING THE SAME
A bonding element and a method for manufacturing the same thereof are provide, wherein the method comprises the following steps: providing a carrier substrate; forming a first metal layer on the carrier substrate; forming a first insulating layer on the first metal layer, wherein the first insulating layer includes a first through hole; forming a first passivation layer and a first conductive layer in the first through hole, wherein the first passivation layer and the first conductive layer in the first through hole form a first connecting bump; forming a first substrate on the first connection bump and the first insulating layer; removing the carrier substrate and the first metal layer to form a first sub-bonding element; and connecting the first sub-bonding element and a second sub-bonding element with a surface of the first passivation of the first connection bump to form the bonding element.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a substrate. A conductive layer is disposed on the substrate and extends in a first direction. An insulating layer is disposed on the conductive layer and exposes at least a portion of the conductive layer through a via hole. The via hole includes a first face extending in a first slope relative to a top face of the conductive layer. A second face extends in a second slope relative to the top face of the conductive layer that is less than the first slope. A redistribution conductive layer includes a first pad area disposed in the via hole. A line area at least partially extends along the first face and the second face. The first face directly contacts the conductive layer. The second face is positioned at a higher level than the first face in a second direction perpendicular to a top face of the substrate.
Stackable via package and method
A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<1/2×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.
Hybrid Integrated Circuit Package
An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.
Dielectric molded indium bump formation and INP planarization
The disclosed technique may be used to electrically and physically connect semiconductor wafers. The wafer may utilize a thick dielectric. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together.
LIGHT-EMITTING PANEL AND DISPLAY DEVICE
Provided are a light-emitting panel and a display device. The light-emitting panel includes a driving substrate and a plurality of light-emitting elements. The driving substrate includes a base substrate, a plurality of driver circuits, and a plurality of photoelectric conversion units. The driver circuits and the photoelectric conversion units are located on the base substrate. A photoelectric conversion unit includes a first doped region and a second doped region. The light-emitting elements are located on a side of the driving substrate. The orthographic projection of a light-emitting element among at least part of the light-emitting elements on the driving substrate is a first projection. An orthographic projection of the photoelectric conversion unit on the driving substrate is located between two adjacent first projections. A driver circuit and the photoelectric conversion unit are each electrically connected to the light-emitting element.