The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP.

The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP.

Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

A bumped solder pad and methods for adding bumps to a solder pad are provided. A substrate is provided having metal layer formed thereon and a solder pad formed from a portion of the metal layer. A surface treatment is applied to the solder pad. The surface treatment is patterned. The surface treatment is etched to produce at least one bump on the solder pad.

Embodiments described herein provide techniques for forming an interconnect structure that includes a bowl shaped pad. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a substrate (e.g., a semiconductor package, a PCB, etc.); and a metal pad over the substrate. The metal pad has a center region and an edge region. A thickness of the center region is smaller than a thickness of the edge region. A thickness of the center region may be non-uniform. The center region may have a bowl shape characterized by a stepped profile. The stepped profile is formed from metal layers arranged as steps. Alternatively, or additionally, the center region may have a bowl shape characterized by a curved profile. A pattern may be formed on or in a surface of the metal pad.

Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.

An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.