Patent classifications
H
ELECTRICITY
Load children
H01
ELECTRIC ELEMENTS
Load children
H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
Load children
2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/10
Bump connectors; Manufacturing methods related thereto
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/12
Structure, shape, material or disposition of the bump connectors prior to the connecting process
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/13
of an individual bump connector
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/13001
Core members of the bump connector
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/131
with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/13101
the principal constituent melting at a temperature of less than 400°C
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/13114
Thallium [Tl] as principal constituent
Filter patents View analytics View as hierarchy Open in page

H01L2224/13114

Connecting conductive pads with post-transition metal and nanoporous metal
11024597 · 2021-06-01 · ·

A first conductive pad is connected to a second conductive pad by using a post-transition metal and a nanoporous metal. An example of the post-transition metal is indium. An example of the nanoporous metal is nanoporous gold. A block of the post-transition metal is formed on the first conductive pad. The block of the post-transition metal is coated with a layer of anti-corrosion material. A block of the nanoporous metal is formed on the second conductive pad. The block of the post-transition metal and the block of the nanoporous metal are thermal compressed to form an alloy between the first conductive pad and the second conductive pad.

Connecting conductive pads with post-transition metal and nanoporous metal
11024597 · 2021-06-01 · ·

A first conductive pad is connected to a second conductive pad by using a post-transition metal and a nanoporous metal. An example of the post-transition metal is indium. An example of the nanoporous metal is nanoporous gold. A block of the post-transition metal is formed on the first conductive pad. The block of the post-transition metal is coated with a layer of anti-corrosion material. A block of the nanoporous metal is formed on the second conductive pad. The block of the post-transition metal and the block of the nanoporous metal are thermal compressed to form an alloy between the first conductive pad and the second conductive pad.

FLIP CHIP PHOTODETECTOR BY USING PLATING AU PILLARS METHOD
20190243079 · 2019-08-08 ·

The present invention is a flip-chip photodetector, comprising a carrier and a back-illuminated chip having a central portion and a peripheral portion, wherein the central portion has a greater thickness than the peripheral portion; the peripheral portion is provided with a plurality of metal pillars connected to the carrier, and the back illuminated chip is connected to the carrier by the plurality of metal pillars; further, the plurality of the metal pillars are provided on the back-illuminated chip by electroless plating.

FLIP CHIP PHOTODETECTOR BY USING PLATING AU PILLARS METHOD
20190243079 · 2019-08-08 ·

The present invention is a flip-chip photodetector, comprising a carrier and a back-illuminated chip having a central portion and a peripheral portion, wherein the central portion has a greater thickness than the peripheral portion; the peripheral portion is provided with a plurality of metal pillars connected to the carrier, and the back illuminated chip is connected to the carrier by the plurality of metal pillars; further, the plurality of the metal pillars are provided on the back-illuminated chip by electroless plating.