H01L2224/1317

SEMICONDUCTOR PACKAGE
20230223353 · 2023-07-13 ·

A semiconductor package includes: a first redistribution layer including a first wiring; a die located on the first redistribution layer; and a shielding structure surrounding the die from an upper surface and side surfaces of the die, wherein the shielding structure includes: a shielding wall that is spaced apart from the side surfaces of the die and surrounds the side surfaces of the die; and a shielding cover that is spaced apart from the upper surface of the die and surrounds the upper surface of the die.

SEMICONDUCTOR PACKAGE INCLUDING UNDERFILL AND METHOD OF FORMING THE SAME
20230154885 · 2023-05-18 ·

A semiconductor package includes a first semiconductor chip on a lower structure. A first underfill is between the first semiconductor chip and the lower structure. The first underfill includes a first portion adjacent to a center region of the first semiconductor chip, and a second portion adjacent to an edge region of the first semiconductor chip. The second portion has a higher degree of cure than the first portion. A plurality of inner connection terminals is between the first semiconductor chip and the lower structure. The plurality of inner connection terminals extends in the first underfill.

3D chip testing through micro-C4 interface

The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.

3D chip testing through micro-C4 interface

The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.

3D chip testing through micro-C4 interface

Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.

3D chip testing through micro-C4 interface

Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.

MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE

A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.

MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE

A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.

Manufacturing method of semiconductor package

A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.

Manufacturing method of semiconductor package

A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.