A thermal interface material may be formed comprising a polymer material and a self-healing constituent. The thermal interface material may be used in an integrated circuit assembly between at least one integrated and a heat dissipation device, wherein the self-healing constituent changes the physical properties of the thermal interface material in response to thermo-mechanical stresses to prevent failure modes from occurring during the operation of the integrated circuit assembly.

A thermal interface material may be formed comprising a polymer material and a self-healing constituent. The thermal interface material may be used in an integrated circuit assembly between at least one integrated and a heat dissipation device, wherein the self-healing constituent changes the physical properties of the thermal interface material in response to thermo-mechanical stresses to prevent failure modes from occurring during the operation of the integrated circuit assembly.

Embodiments described herein provide techniques for forming an interconnect structure that includes a bowl shaped pad. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a substrate (e.g., a semiconductor package, a PCB, etc.); and a metal pad over the substrate. The metal pad has a center region and an edge region. A thickness of the center region is smaller than a thickness of the edge region. A thickness of the center region may be non-uniform. The center region may have a bowl shape characterized by a stepped profile. The stepped profile is formed from metal layers arranged as steps. Alternatively, or additionally, the center region may have a bowl shape characterized by a curved profile. A pattern may be formed on or in a surface of the metal pad.

Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate having a plurality of conductive through-glass vias (TGV); a magnetic core inductor including: a first conductive TGV at least partially surrounded by a magnetic material; and a second conductive TGV electrically coupled to the first TGV; a first die in a first dielectric layer, wherein the first dielectric layer is on the glass substrate; and a second die in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the second die is electrically coupled to the magnetic core inductor.