The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP.

The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP.

An electronic apparatus including a substrate, a plurality of first bonding pads, an electronic device, and a first spacer is provided. The first bonding pads are disposed on the substrate. The electronic device is disposed on the substrate and electrically connected to the first bonding pads. The first spacer is disposed between the electronic device and the substrate. The electronic device is capable of effectively controlling a height and uniformity of a gap between the electronic device and the substrate, so as to prevent the electronic device from being tilted and ensure the electronic device to have a favorable structural reliability.

An electronic apparatus including a substrate, a plurality of first bonding pads, an electronic device, and a first spacer is provided. The first bonding pads are disposed on the substrate. The electronic device is disposed on the substrate and electrically connected to the first bonding pads. The first spacer is disposed between the electronic device and the substrate. The electronic device is capable of effectively controlling a height and uniformity of a gap between the electronic device and the substrate, so as to prevent the electronic device from being tilted and ensure the electronic device to have a favorable structural reliability.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.

A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).

The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).