Provided are a Cu column, a Cu core column, a solder joint, and a through-silicon via, which have the low Vickers hardness and the small arithmetic mean roughness. For the Cu column 1 according to the present invention, its purity is equal to or higher than 99.9% and equal to or lower than 99.995%, its arithmetic mean roughness is equal to or less than 0.3 μm, and its Vickers hardness is equal to or higher than 20 HV and equal to or less than 60 HV. Since the Cu column 1 is not melted at a melting temperature in the soldering and a definite stand-off height (a space between the substrates) can be maintained, it is preferably applied to the three dimensional mounting or the pitch narrowing mounting.

An electronic assembly, and a method for making the electronic assembly, includes a first electronic component, a second electronic component, and a plurality of interconnects. The plurality of interconnects electrically couple the first electronic component to the second electronic component. Each of the plurality of interconnects comprise one of a plurality of first magnetic components in physical alignment with an associated one of a plurality of second magnetic components, the plurality of second magnetic components being components of one of the second electronic component and the plurality of interconnects.

An electronic assembly, and a method for making the electronic assembly, includes a first electronic component, a second electronic component, and a plurality of interconnects. The plurality of interconnects electrically couple the first electronic component to the second electronic component. Each of the plurality of interconnects comprise one of a plurality of first magnetic components in physical alignment with an associated one of a plurality of second magnetic components, the plurality of second magnetic components being components of one of the second electronic component and the plurality of interconnects.

Provided are a Cu column, a Cu core column, a solder joint, and a through-silicon via, which have the low Vickers hardness and the small arithmetic mean roughness. For the Cu column 1 according to the present invention, its purity is equal to or higher than 99.9% and equal to or lower than 99.995%, its arithmetic mean roughness is equal to or less than 0.3 m, and its Vickers hardness is equal to or higher than 20 HV and equal to or less than 60 HV. Since the Cu column 1 is not melted at a melting temperature in the soldering and a definite stand-off height (a space between the substrates) can be maintained, it is preferably applied to the three dimensional mounting or the pitch narrowing mounting.

A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact.

A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact.

A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 m). The subarray probe tips may be on a pitch at or less than fifty microns (50 m). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.

A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 m). The subarray probe tips may be on a pitch at or less than fifty microns (50 m). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.

An electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. A second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.