An object of the present technology is to prevent damage in a bonded portion between a semiconductor chip and a substrate in a semiconductor device in which the semiconductor chip is mounted on the substrate.

A terminal is disposed between an electrode of an element and an electrode of a substrate on which the element is mounted, and electrically connects the electrode of the element and the electrode of the substrate. The terminal includes a plurality of unit lattices and a coupling portion. The unit lattices included in the terminal are formed by bonding a plurality of beams in a cube shape. The coupling portion included in the terminal couples adjacent unit lattices among the plurality of unit lattices.

A semiconductor-mounted product includes a semiconductor package, a wiring substrate, four or more soldered portions, and a resin-reinforced portion. Each of the soldered portions electrically connects the semiconductor package to the wiring of the wiring substrate. The resin-reinforced portion is formed on a side surface of each of the soldered portions. Each of the soldered portions has a first solder region formed closer to the semiconductor package than the wiring substrate and a second solder region formed closer to the wiring substrate than the semiconductor package. A proportion of a void present in a polygon connecting centers of soldered portions located at outermost positions among the soldered portions to a sum of the void and the resin-reinforced portion is from 10% to 99%, inclusive.

A semiconductor-mounted product includes a semiconductor package, a wiring substrate, four or more soldered portions, and a resin-reinforced portion. Each of the soldered portions electrically connects the semiconductor package to the wiring of the wiring substrate. The resin-reinforced portion is formed on a side surface of each of the soldered portions. Each of the soldered portions has a first solder region formed closer to the semiconductor package than the wiring substrate and a second solder region formed closer to the wiring substrate than the semiconductor package. A proportion of a void present in a polygon connecting centers of soldered portions located at outermost positions among the soldered portions to a sum of the void and the resin-reinforced portion is from 10% to 99%, inclusive.

An electronic device with stud bumps is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, wherein the carrier board has at least one recess in the upper surface, and wherein at least one of the stud bumps reaches into the recess.

An electronic device with stud bumps is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, wherein the carrier board has at least one recess in the upper surface, and wherein at least one of the stud bumps reaches into the recess.

Disclosed herein is a semiconductor device including a conductive member that has a main surface facing in a thickness direction, a semiconductor element that has a plurality of pads facing the main surface, a plurality of electrodes that are individually formed with respect to the plurality of pads and protrude from the plurality of pads toward the main surface, and a bonding layer for electrically bonding the main surface to the plurality of electrodes. The bonding layer includes a first region having conductivity and a second region having electrical insulation. The first region includes a metal portion. At least a part of the second region includes a resin portion.

An electronic device with stud bumps is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, wherein the carrier board has at least one recess in the upper surface, and wherein at least one of the stud bumps reaches into the recess.

An electronic device with stud bumps is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, wherein the carrier board has at least one recess in the upper surface, and wherein at least one of the stud bumps reaches into the recess.

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

An electronic device is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface of the carrier board, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface of the carrier board, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, and wherein a laminated polymer hood at least partly covers the top side of the electronic chip and extends onto the upper surface of the carrier board.