A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.

An apparatus includes an Integrated Circuit (IC). A first pillar includes a first end and a second end. The first end is connected to the IC and the second end includes a first attachment point collinear with a first central axis of the first pillar. The first attachment point includes a first solder volume capacity. A second pillar includes a third end and a fourth end. The third end is connected to the IC and the fourth end includes a second attachment point disposed on a side of the second pillar facing the first pillar. The second attachment point includes a second solder volume capacity being less than the first solder volume capacity. A first distance between the first end and the second end is less than a second distance between the third end and the fourth end.

An apparatus includes an Integrated Circuit (IC). A first pillar includes a first end and a second end. The first end is connected to the IC and the second end includes a first attachment point collinear with a first central axis of the first pillar. The first attachment point includes a first solder volume capacity. A second pillar includes a third end and a fourth end. The third end is connected to the IC and the fourth end includes a second attachment point disposed on a side of the second pillar facing the first pillar. The second attachment point includes a second solder volume capacity being less than the first solder volume capacity. A first distance between the first end and the second end is less than a second distance between the third end and the fourth end.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.

According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.

An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

A manufacturing method comprises preparing a bonding substrate having bumps thereon; preparing a mounted member having external conductive members; applying a fixing material to the surface of the bonding substrate and/or to a surface of the mounted member; and fixing the bonding substrate and the mounted member with the fixing material such that the bumps contact the external conductive members. The fixing material is prepared to contain a first compound and a second compound, each having respective viscosities which change depending on their respective temperature profiles; and applying the fixing material to the bonding substrate and/or the mounted member at a temperature lower than a first temperature, and the fixing comprises pressing the bonding substrate against the mounted member when the fixing material has a temperature lower than the first temperature; and heating the fixing material to a temperature higher than the second temperature and curing the fixed material.