A device package with a reduced foot print may include a substrate and a through-substrate via extending from a top surface to a bottom surface of the substrate. The assembly may also include a trace and a contact pad on the top and bottom surfaces of the substrate and electrically coupled to the through-substrate via. An encapsulated die above the substrate may be electrically coupled to the trace. A joint below the substrate may be electrically coupled to the contact pad. A sidewall of the through-substrate via may be exposed. At least a portion of the through-substrate via may be within an outer side boundary of the substrate. Also, the trace and the contact pad may be within the outer side boundary of the substrate.

A wiring substrate includes a first insulating layer including a first through-hole formed through the first insulating layer in a thickness direction, a wiring layer formed on a lower surface of the first insulating layer, and a via wiring filled in the first through-hole and connected to the wiring layer, the via wiring having such a shape that it gradually becomes thinner from one side close to the lower surface of the first insulating layer toward the other side close to an upper surface of the first insulating layer, the via wiring including a first recess formed in an upper end surface of the via wiring. An upper end portion of the via wiring is an electrode pad for electric connection with an electronic component.

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate of which may be flexible. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart label and may be formed via roller or other methods.

A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.

A wiring board includes a base board and a plurality of wiring layers formed of a resin insulating film on the base board, wherein at least one of the wiring layers includes a fine wiring, a barrier film, which is not in contact with the fine wiring, is formed at a more outer side than the base board than the wiring layer including the fine wiring, and different types of resin insulating films are used for a wiring layer at an inner side of the barrier film close to the base board and a wiring layer at an outer side of the barrier film, respectively.

A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.

A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.

Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

An electronics package includes a thermal lid over a flip chip component such that the thermal lid is in contact with a surface of a flip chip component and one or more thermal vias in a substrate on which the flip chip component is mounted. The thermal lid dissipates heat from the flip chip component by way of the thermal vias to improve the thermal performance of the electronics package.