A semiconductor package includes a first semiconductor chip including upper signal pads and upper dummy pads. A second semiconductor chip is on the first semiconductor chip, and includes lower signal pads and lower dummy pads. First conductive bumps are between the upper signal pads and the lower signal pads. Second conductive bumps are between the upper dummy pads and the lower dummy pads. The upper dummy pads include merged pads covering a plurality of adjacent lower dummy pads. A plurality of metal plating layers are disposed on each of the merged pads in areas respectively corresponding to the plurality of adjacent lower dummy pads. The second conductive bumps include a plurality of conductive bumps respectively disposed between the plurality of first metal plating layers and the plurality of adjacent lower dummy pads.

A system on a chip (SOC) device includes a substrate, processing circuitry formed on the substrate, and noise reduction circuitry formed on the processing circuitry. The noise reduction circuitry is configured to reduce noise caused by variations in current consumed by the processing circuitry. The noise reduction circuitry includes a decoupling capacitor, which includes (i) two or more first layers, (ii) one or more second layers interleaved between the first layers, (iii) dielectric layers formed between adjacent first and second layers and configured to electrically isolate between the adjacent first and second layers, (iv) a first contact, which is electrically connected to the first layers so as to form a first electrode of the decoupling capacitor, and (v) a second contact, which is electrically connected to the second layers so as to form a second electrode of the decoupling capacitor.

A fan-out package includes at least one semiconductor die attached to an interposer structure. a molding compound die frame laterally surrounding the at least one semiconductor die and including a molding compound material, and at least one stress buffer structure located on the interposer structure and including a stress buffer material having a first Young's modulus. The molding compound die frame includes a molding compound material having a second Young's modulus that is greater than the first Young's modulus.

A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.

A light-emitting module includes: a first flexible insulating substrate having a plurality of conductor patterns formed on a surface; and a light-emitting element having a first electrode placed in a first region on a surface facing the first insulating substrate and connected to a first conductor pattern out of the plurality of conductor patterns through a first bump, and a second electrode placed in a second region different from the first region on a surface facing the first insulating substrate and connected to a second conductor pattern different from the first conductor pattern through a second bump, wherein a ratio of a distance from the first region to a contact point between the first bump and the first conductor pattern against a distance from the first electrode to a position where an outer edge of the first conductor pattern intersects with an outer edge of the second region is equal to or greater than 0.1.

Provided is a method of manufacturing a semiconductor device including a bump interconnect structure. In the method of manufacturing the semiconductor device, a first substrate including a connection pad is formed, and a bump including a solder layer and a metal post protruding from the solder layer are formed on the connection pad. A second substrate including a bump land may be formed. The first substrate may be disposed on the second substrate so that a protruding end of the metal post contacts the bump land, and the solder layer may be reflowed. Accordingly, it possible to interconnect the metal post to the bump land.

An electronic apparatus including a package substrate and a structure disposed on and electrically connected to the package substrate through conductive bumps is provided. The material of the conductive bumps includes a bismuth (Bi) containing alloy or an indium (In) containing alloy. In some embodiments, the bismuth (Bi) containing alloy includes SnAgCuBi alloy. In some embodiments, a concentration of bismuth (Bi) contained in the SnAgCuBi alloy ranges from about 1 wt % to about 10 wt %. Methods for forming the SnAgCuBi alloy are also provided.

A light-emitting module includes: a first flexible insulating substrate having a plurality of conductor patterns formed on a surface; and a light-emitting element having a first electrode placed in a first region on a surface facing the first insulating substrate and connected to a first conductor pattern out of the plurality of conductor patterns through a first bump, and a second electrode placed in a second region different from the first region on a surface facing the first insulating substrate and connected to a second conductor pattern different from the first conductor pattern through a second bump, wherein a ratio of a distance from the first region to a contact point between the first bump and the first conductor pattern against a distance from the first electrode to a position where an outer edge of the first conductor pattern intersects with an outer edge of the second region is equal to or greater than 0.1.

An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die; and at least one device within the build-up carrier disposed in an area void of a layer of patterned conductive material. A method and an apparatus including a computing device including a package including a microprocessor are also disclosed.

An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die; and at least one device within the build-up carrier disposed in an area void of a layer of patterned conductive material. A method and an apparatus including a computing device including a package including a microprocessor are also disclosed.