Patent classifications
H01L2224/40237
Semiconductor device
A semiconductor device includes: a first semiconductor chip including a junction-type FET; a second semiconductor chip including a MOSFET; and a junction-type FET adjustment resistor disposed between a gate electrode of the junction-type FET and a source electrode of the MOSFET. The junction type FET and the MOSFET are cascode-connected. The junction-type FET adjustment resistor includes a first resistance circuit for a switching on operation and a second resistance circuit for a switching off operation.
Semiconductor component and method of manufacture
In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. A first electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a first lead. A second electrical interconnect is coupled between the control terminal of the semiconductor device and a second lead.
SEMICONDUCTOR MODULE
A semiconductor module according to the present disclosure includes: an insulating substrate; a first conductor disposed on the insulating substrate; a second conductor disposed on the insulating substrate; a first semiconductor element disposed on the first conductor; a second semiconductor element disposed on the second conductor; a first busbar connected to the first conductor in a region between the first semiconductor element and the second semiconductor element; a second busbar connected to the second semiconductor element; and an output busbar connecting the first semiconductor element to the second conductor and connected to the second conductor in the region between the first semiconductor element and the second semiconductor element. The output busbar is disposed at least partially overlapping the first busbar, and in an overlap region between the output busbar and the first busbar, the output busbar is located above the first busbar.
Integrated circuit chip packaging including a heat sink topped cavity
An electrical circuit device includes a circuit board including a cavity extending from a top surface of the circuit board to an embedded conductor, an integrated circuit chip in the cavity, an electrical connection between the integrated circuit chip and the embedded conductor, a thermal slug disposed over a top surface of the integrated circuit chip, and a heat sink mounted to an outer surface of the thermal slug for transferring a thermal energy away from the circuit board, the heat sink extending above a top surface of the circuit board.
INTEGRATED CIRCUIT CHIP PACKAGING
A method of mounting an integrated circuit chip to a circuit board includes placing the integrated circuit chip into a cavity extending from a surface of the circuit board to an embedded conductor, electrically connecting the integrated circuit chip to the embedded conductor, and disposing a heat sink over a surface of the integrated circuit chip. The electrically connecting the integrated circuit chip to the embedded conductor includes flip chip mounting of the integrated circuit chip within the cavity.
INTEGRATED CIRCUIT CHIP PACKAGING
A method of mounting an integrated circuit chip to a circuit board includes placing the integrated circuit chip into a cavity extending from a surface of the circuit hoard to an embedded conductor, electrically connecting the integrated circuit chip to the embedded conductor, and disposing a heat sink over a surface of the integrated circuit chip.
SEMICONDUCTOR DEVICE
A semiconductor device includes: a first semiconductor chip including a junction FET; a second semiconductor chip including a MOSFET; and a junction-type FET adjustment resistor disposed between a gate electrode of the junction-type FET and a source electrode of the MOSFET. The junction type FET and the MOSFET are cascode-connected. The junction FET adjustment resistor includes a first resistance circuit for a switching on operation and a second resistance circuit for a switching off operation.
Integrated circuit chip packaging
A method of mounting an integrated circuit chip to a circuit board includes placing the integrated circuit chip into a cavity extending from a surface of the circuit board to an embedded conductor, and electrically connecting the integrated circuit chip to the embedded conductor.
SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. A first electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a first lead. A second electrical interconnect is coupled between the control terminal of the semiconductor device and a second lead.
Semiconductor component and method of manufacture
In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. The control terminal of the first electrical interconnect is coupled to a first lead by a first electrical interconnect. A second electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a second lead. The second current carrying terminal of the first semiconductor device is coupled to the device receiving structure or to the interconnect structure.