Patent classifications
H01L2224/45639
BONDING WIRE FOR SEMICONDUCTOR DEVICES
There is provided a bonding wire for semiconductor devices that exhibits a favorable bondability even when being applied to wedge bonding at the room temperature, and also achieves an excellent bond reliability. The bonding wire includes a core material of Cu or Cu alloy (hereinafter referred to as a “Cu core material”), and a coating containing a noble metal formed on a surface of the Cu core material. A concentration of Cu at a surface of the wire is 30 to 80 at%.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.
CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT
In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT
In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
Half Bridge Circuit, Method of Operating a Half Bridge Circuit and a Half Bridge Circuit Package
A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.
CONFIGURABLE LEADED PACKAGE
A semiconductor package includes a base insulating layer; a semiconductor die attached to a portion of the base insulating layer; and a first continuous lead electrically connected to the semiconductor die. The first continuous lead includes a first lateral extension on a first surface of the base insulating layer, a second lateral extension on a second surface of the base insulating layer, and a connecting portion between the first lateral extension and the second lateral extension. The connecting portion penetrates through the base insulating layer.
CONFIGURABLE LEADED PACKAGE
A semiconductor package includes a base insulating layer; a semiconductor die attached to a portion of the base insulating layer; and a first continuous lead electrically connected to the semiconductor die. The first continuous lead includes a first lateral extension on a first surface of the base insulating layer, a second lateral extension on a second surface of the base insulating layer, and a connecting portion between the first lateral extension and the second lateral extension. The connecting portion penetrates through the base insulating layer.
BONDING WIRE
There is provided a metal-coated Al bonding wire which can provide a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the metal-coated Al bonding wire is operated. The bonding wire includes a core wire of Al or Al alloy, and a coating layer of Ag, Au or an alloy containing them formed on the outer periphery of the core wire, and the bonding wire is characterized in that when measuring crystal orientations on a cross-section of the core wire in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <111> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30 to 90% among crystal orientations in the wire longitudinal direction. Preferably, the surface roughness of the wire is 2 μm or less in terms of Rz.
BONDING WIRE
There is provided a metal-coated Al bonding wire which can provide a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the metal-coated Al bonding wire is operated. The bonding wire includes a core wire of Al or Al alloy, and a coating layer of Ag, Au or an alloy containing them formed on the outer periphery of the core wire, and the bonding wire is characterized in that when measuring crystal orientations on a cross-section of the core wire in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <111> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30 to 90% among crystal orientations in the wire longitudinal direction. Preferably, the surface roughness of the wire is 2 μm or less in terms of Rz.
Die bonding material, light-emitting device, and method for producing light-emitting device
The present invention provides a die bonding material containing the following component (A) and a solvent and having a refractive index (nD) at 25° C. of 1.41 to 1.43 and a thixotropic index of 2 or more, a light-emitting device including an adhesive member derived from the die bonding material, and a method for producing the light-emitting device. The die bonding material of the present invention is preferably used for fixing a light emitting element at a predetermined position. Component (A): a curable polysilsesquioxane compound having a repeating unit represented by the following formula (a-1) and satisfying predetermined requirements related to .sup.29Si-NMR and mass average molecular weight (Mw)
R.sup.1-D-SiO.sub.3/2 (a-1) [wherein R.sup.1 represents a fluoroalkyl group represented by a compositional formula: C.sub.mH.sub.(2m−n+1)F.sub.n; m represents an integer of 1 to 10, and n represents an integer of 2 to (2m+1); and D represents a linking group (excluding an alkylene group) for connecting R.sup.1 and Si, or a single bond].