There is provided a novel Cu bonding wire that achieves a favorable FAB shape and reduces a galvanic corrosion in a high-temperature environment to achieve a favorable bond reliability of the 2nd bonding part. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of 90 atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.0 or less where X is defined as an average value of a ratio of a Pd concentration C.sub.Pd (atomic %) to an Ni concentration C.sub.Ni (atomic %), C.sub.Pd/C.sub.Ni, for all measurement points in the coating layer, and the total number of measurement points in the coating layer whose absolute deviation from the average value X is 0.3X or less is 50% or more relative to the total number of measurement points in the coating layer.

In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

In a described example, an apparatus includes: a package substrate including a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead and a third lead; and a semiconductor die including a temperature sensor mounted on the die pad. The semiconductor die includes a first metallization layer being a metallization layer closest to the active surface of the semiconductor die, and successive metallization layers overlying the previous metallization layer, the metallization layers including a respective conductor layer in a dielectric material for the particular metallization layer and conductive vias; and the temperature sensor formed of the conductor layer in an uppermost metallization layer and coupled to the second lead and to the third lead. The semiconductor die includes a high voltage ring formed in the uppermost metallization layer, spaced from and surrounding the temperature sensor.

In a described example, an apparatus includes: a package substrate including a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead and a third lead; and a semiconductor die including a temperature sensor mounted on the die pad. The semiconductor die includes a first metallization layer being a metallization layer closest to the active surface of the semiconductor die, and successive metallization layers overlying the previous metallization layer, the metallization layers including a respective conductor layer in a dielectric material for the particular metallization layer and conductive vias; and the temperature sensor formed of the conductor layer in an uppermost metallization layer and coupled to the second lead and to the third lead. The semiconductor die includes a high voltage ring formed in the uppermost metallization layer, spaced from and surrounding the temperature sensor.

There is provided a bonding wire for semiconductor devices that exhibits a favorable bondability even when being applied to wedge bonding at the room temperature, and also achieves an excellent bond reliability. The bonding wire includes a core material of Cu or Cu alloy (hereinafter referred to as a “Cu core material”), and a coating containing a noble metal formed on a surface of the Cu core material. A concentration of Cu at a surface of the wire is 30 to 80 at%.

A semiconductor package assembly and method of manufacturing is provided. The assembly includes a semiconductor package and a moulding resin case encapsulating the semiconductor package. The package includes a lead frame having a first frame side and a second frame side opposite to the first frame side; a silicon die structure having a first die side and a second die side opposite to the first side, the silicon die structure being mounted with its second die side on the first frame side of the lead frame; one or more bond wires electrically connecting the silicon die structure with the lead frame; as well as a coating layer covering the semiconductor package from the encapsulating moulding resin case, the coating layer being composed of two or more different amorphous layer coatings. The use of a coating layer covering the complete semiconductor package forming the encapsulating moulding resin case prevents any corrosion.

A semiconductor package assembly and method of manufacturing is provided. The assembly includes a semiconductor package and a moulding resin case encapsulating the semiconductor package. The package includes a lead frame having a first frame side and a second frame side opposite to the first frame side; a silicon die structure having a first die side and a second die side opposite to the first side, the silicon die structure being mounted with its second die side on the first frame side of the lead frame; one or more bond wires electrically connecting the silicon die structure with the lead frame; as well as a coating layer covering the semiconductor package from the encapsulating moulding resin case, the coating layer being composed of two or more different amorphous layer coatings. The use of a coating layer covering the complete semiconductor package forming the encapsulating moulding resin case prevents any corrosion.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.