A semiconductor package according to the present disclosure includes: a plurality of semiconductor chips that include a system on chip (SoC) in which a plurality of integrated circuits including a processor core and a microcomputer are integrated on a single chip; a power management integrated circuit (IC) for performing power management on the plurality of semiconductor chips; a plurality of shunt resistors each of which is mounted in series on a different one of power wires connecting the power management IC and the plurality of semiconductor chips; two output terminals; and a single selector that outputs voltages at both ends of a shunt resistor to an outside via the two output terminals, the shunt resistor being selected from among the plurality of shunt resistors. The power management IC, the plurality of semiconductor chips, the plurality of shunt resistors, and the single selector are mounted inside a single package.

Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.

A die package includes a semiconductor die, a passive component, a molding compound and a redistribution layer (RDL). The semiconductor die includes a first bonding pad. The passive component includes a second bonding pad. The molding compound encloses the semiconductor die and the passive component. The RDL is disposed over the semiconductor die and the passive component and electrically connecting the first bonding pad with the second bonding pad. The semiconductor die is vertically overlapped with the passive component.

A package construction includes: a die pad, and a suspension lead remaining portion connected to the die pad. Here, an offset portion is provided from a peripheral edge portion of the die pad to the suspension lead remaining portion. Also, the suspension lead remaining portion has: a first end portion connected to the die pad, and a second end portion opposite the first end portion. Further, the second end portion of the suspension lead remaining portion is exposed from the side surface of the sealing body at a position spaced apart from each of the upper surface and the lower surface.

A semiconductor chip including a main electrode and a control electrode is bonded to a substrate. A wiring chip including a first electrode, a second electrode and a wiring is bonded to the substrate. A main electrode member is bonded to the main electrode. A control electrode member is bonded to the second electrode. The control electrode is bonded to the first electrode with a connection member. The semiconductor chip, the substrate, the wiring chip, the main electrode member, the control electrode member and the connection member are putted into a mold and are sealed with sealing material by injecting the sealing material into the mold in a state that distal end surfaces of the main electrode member and the control electrode member are pressed against a buffer material provided between the main electrode member/the control electrode member and the mold. The sealing material is not ground.

A semiconductor device includes: a first lead; a first semiconductor element mounted on the first lead; and a sealing resin that covers the first semiconductor element, wherein the first lead includes: a first die pad having a first main surface and a first back surface facing opposite sides to each other in a thickness direction; a second die pad arranged side by side with the first die pad in a first direction orthogonal to the thickness direction, and located on a side of the first main surface with respect to the first die pad in the thickness direction; and a connecting portion connected to the first die pad and the second die pad, and wherein the first back surface is exposed from the sealing resin.

Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.

Some embodiments include a method, comprising: attaching a carrier substrate to a side of at least one semiconductor substrate, the at least one semiconductor substrate including photodetectors on the side; thinning the at least one semiconductor substrate while the at least one semiconductor substrate is attached to the carrier substrate; attaching an optical substrate to the at least one semiconductor substrate while the at least one semiconductor substrate is attached to the carrier substrate; and removing the carrier substrate from the at least one semiconductor substrate.

An apparatus is provided which comprises: a substrate; a stacked ring structure disposed on the substrate, the stacked ring structure comprising a first ring and a second ring; a first partial through-mold-via (TMV) formed on the first ring; and a second partial TMV formed on the second ring, wherein the first ring and the second ring are stacked such that the first partial TMV is aligned on top of the second partial TMV.

An apparatus is provided which comprises: a substrate; a stacked ring structure disposed on the substrate, the stacked ring structure comprising a first ring and a second ring; a first partial through-mold-via (TMV) formed on the first ring; and a second partial TMV formed on the second ring, wherein the first ring and the second ring are stacked such that the first partial TMV is aligned on top of the second partial TMV.