A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

First and second switching regions include first and second gate electrodes respectively. Channel currents of the first and second switching regions are controlled according to electric charge amounts supplied by control signals input to the first and second gate electrodes respectively. The second switching region is connected in parallel with the first switching region. A control section outputs a first control signal for turning-on the first switching region to the first gate electrode and a second control signal for turning-on the second switching region to the second gate electrode. The control section stops outputting the second control signal after a first predetermined period elapses from a start of outputting the first and second control signals, and outputs the second control signal after a second predetermined period elapses from a stop of outputting the second control signal.

First and second switching regions include first and second gate electrodes respectively. Channel currents of the first and second switching regions are controlled according to electric charge amounts supplied by control signals input to the first and second gate electrodes respectively. The second switching region is connected in parallel with the first switching region. A control section outputs a first control signal for turning-on the first switching region to the first gate electrode and a second control signal for turning-on the second switching region to the second gate electrode. The control section stops outputting the second control signal after a first predetermined period elapses from a start of outputting the first and second control signals, and outputs the second control signal after a second predetermined period elapses from a stop of outputting the second control signal.

A semiconductor device includes: a base plate including a metallic base plate and an insulating film provided on the metallic base plate; a semiconductor chip provided on the base plate; a control board disposed above the semiconductor chip; and a relay terminal connected to a signal electrode of the semiconductor chip through a signal line wire, extending to the control board, and connected to the control board, wherein the relay terminal is directly fixed to the insulating film of the base plate.

A semiconductor device includes: a base plate including a metallic base plate and an insulating film provided on the metallic base plate; a semiconductor chip provided on the base plate; a control board disposed above the semiconductor chip; and a relay terminal connected to a signal electrode of the semiconductor chip through a signal line wire, extending to the control board, and connected to the control board, wherein the relay terminal is directly fixed to the insulating film of the base plate.

A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.