A semiconductor device includes a substrate, a conductive part, a controller module and a sealing resin. The substrate has a substrate obverse surface and a substrate reverse surface facing away from each other in a z direction. The conductive part is made of an electrically conductive material on the substrate obverse surface. The controller module is disposed on the substrate obverse surface and electrically connected to the conductive part. The sealing resin covers the controller module and at least a portion of the substrate. The conductive part includes an overlapping wiring trace having an overlapping portion overlapping with the electronic component as viewed in the z direction. The overlapping portion of the overlapping wiring trace is not electrically bonded to the controller module.

An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

An integrated circuit chip carrier includes a wall surrounding a cavity. The wall includes one or more levels where each level is formed from a layer of a resin around a block. The block is made of a material different from the resin. The block is removed to open the cavity.

A semiconductor package includes a package substrate having a first side portion adjacent to a first edge, and a second side portion adjacent to a second edge opposite the first edge; a plurality of first substrate pads on the package substrate at the first side portion of the package substrate; a first chip on the package substrate; a second chip stacked on the first chip in a step-wise manner to result in a first exposure region exposing a portion of a surface of the first chip with respect to the second chip due to the step-wise stacking, the first exposure region being adjacent to a first edge of the first chip; a plurality of first bonding pads on a first portion of the first exposure region, the first portion of the first exposure region being adjacent to the first edge of the first chip; a plurality of second bonding pads on a second portion of the first exposure region, the second portion of the first exposure region further from the first edge of the first chip than the first portion of the first exposure region is to the first edge of the first chip, the plurality of second bonding pads being electrically insulated from any circuit components in the first chip; a plurality of third bonding pads on a surface of the second chip; and a plurality of bonding wires electrically connecting the third bonding pads to the first substrate pads via the second bonding pads.

Before a semiconductor die of a brittle III-V compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

A semiconductor module arrangement includes a housing and at least one pair of semiconductor substrates arranged inside the housing. Each pair of semiconductor substrates includes first and second semiconductor substrates. The first semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The second semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential, and the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential that is opposite to the first electrical potential.

According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.

A semiconductor device includes an insulation substrate including a circuit pattern, semiconductor chips mounted on the circuit pattern, a wire connecting between the semiconductor chips and between the semiconductor chip and the circuit pattern, and a conductive material serving as a conductor formed integrally with the wire.

A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

Electromagnetic shields for electronic devices, and particularly electromagnetic shields with bonding wires for sub-modules of electronic devices are disclosed. Electronic modules are disclosed that include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged on or over the sub-modules. Bonding wires are disclosed that form one or more bonding wire walls along the substrate. The one or more bonding wire walls may be located between sub-modules of a module and about peripheral boundaries of the module. The electromagnetic shield may be electrically coupled to ground by way of the one or more bonding wire walls. Portions of the electromagnetic shield and the one or more bonding wire walls may form divider walls that are configured to reduce electromagnetic interference between the sub-modules or from external sources.