A chip structure, a packaging structure and a manufacturing method of the chip structure are provided. The chip structure includes a base and an electrically conductive interconnection layer. An upper surface of the base is provided with a plurality of bonding pads, and at least two of the bonding pads have same properties. The electrically conductive interconnection layer includes a plurality of electrically conductive interconnection structures. The electrically conductive interconnection structure electrically connects the bonding pads having same properties, and is configured to be electrically connected with a pin on a packaging substrate.

The invention concerns an assembly comprising: a fuel supply circuit (15, 15a, 15b) configured to supply fuel to a turbine heat engine, an electronic module (14, 14a, 14b), a power source (13, 13a, 13b) for supplying power to the electronic module (14, 14a, 14b), and a heat exchanger (16, 16a, 16b) positioned to allow a flow of heat from the electronic module (14, 14a, 14b) to the fuel supply circuit (15, 15a, 15b), the assembly being characterised in that the electronic module (14, 14a, 14b) comprises a phase-change material (PCM), configured to change state when the temperature of same reaches a predetermined phase-change temperature (Tf).

A transistor outline housing is provided that includes a header for an optoelectronic component. The header has electrical feedthroughs in the form of connection pins embedded in a potting compound. The header has a recess in which at least one of the connection pins in one of the feedthroughs extends out of the lower surface of the header.

An object is to provide a power module in which adhesion of a sealing resin is sufficient and which is highly reliable. The power module includes: an insulative board in which a pattern of a conductor layer is formed on a ceramic plate; power semiconductor elements placed on the insulative board; lead frames each in a plate shape connecting from electrodes of the power semiconductor elements to screw-fastening terminal portions; and a sealing resin portion that seals connection portions between the power semiconductor elements and the lead frames, and regions around the connection portions; wherein, in the lead frames, opening portions are formed at positions where each of the lead frames at least partly overlaps, in planar view, with a portion of the insulative board on which the conductor layer is not formed.

Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.

Embodiments described herein provide an electronic device having an integrated circuit disposed in a surface mount package. The surface mount integrated circuit package comprises a first pin and a second pin of the integrated circuit configured to couple the integrated circuit to a first terminal and a second terminal disposed on a circuit board. The first pin and second pin define a first connector and a second connector of a differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board. The surface mount integrated circuit package comprises an isolation stud disposed between the first pin and the second pin. The isolation stud is disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.

A power semiconductor module contains a power semiconductor assembly, a housing which in a housing side with an outer surface has a recess with a direction of passage in the normal direction of the outer surface, having an internal contact device which has an electrically conducting contact inside the housing to an external connection element, designed as a load terminal element, with one section in the recess and having a spring element. The connection element is designed as a rigid metallic shaped body with an inner and an outer contact surface, and the outer contact surface is accessible from the outside, and the connection element is connected to the housing via an electrically insulating and mechanically elastic retaining device such that the connection element is moveable in the direction of passage, and wherein the spring element is arranged and designed in such a way that the spring action thereof acts directly or indirectly on the connection element in the direction of passage.

An upper conductor portion having a thickness A larger than a thickness B of a lower conductor portion, the upper conductor portion including a circuit pattern on which semiconductor chips are disposed and an outer peripheral pattern provided on an outer peripheral side of the circuit pattern at a certain gap, the outer peripheral pattern of the upper conductor portion, an outer peripheral portion of an insulating layer, and an outer peripheral portion of the lower conductor portion are fixed to a concave portion formed in the inner peripheral portion of the peripheral wall portion of a case, a collar portion projecting outward from the outer peripheral portion of the peripheral wall portion of the case is formed, and the attachment holes, through which the radiation fins are attachable, are formed in the collar portion.

A heat and shock resistant integrated circuit (IC) of the present invention includes a base material, a metal layer disposed on the base material, a silicon die disposed on the metal layer, additive material disposed on the base material, gas filled filler material disposed between the additive material and the silicon die, and first traces electrically connecting the silicon die to the additive material. Packing of the integrated circuit provides exceptional thermal stress relief and impact protection of circuitry within the packaging.

A method and a device for establishing a wire connection between a first contact surface and at least one further contact surface. A contact end of a wire is positioned in a contact position relative to the first contact surface with a wire guiding tool. Subsequently, a mechanical, electrically conductive connection is established between the first contact surface and the contact end with a first solder material connection, and subsequently the wire guiding tool is moved to the further contact surface thus forming a wire section and establishing a further mechanical, electrically conductive connection between the wire section end and the further contact surface with a further solder material connection.