A battery system has a battery cell including a can, and a ceramic substrate, including a patterned metallized surface, mounted to the can via a thermally conductive adhesive. The battery system also has a monolithic integrated circuit that measures and transmits data about the cell mounted to the patterned metallized surface such that the ceramic substrate and monolithic integrated circuit are electrically isolated from one another.

A power semiconductor module contains a power semiconductor assembly, a housing which in a housing side with an outer surface has a recess with a direction of passage in the normal direction of the outer surface, having an internal contact device which has an electrically conducting contact inside the housing to an external connection element, designed as a load terminal element, with one section in the recess and having a spring element. The connection element is designed as a rigid metallic shaped body with an inner and an outer contact surface, and the outer contact surface is accessible from the outside, and the connection element is connected to the housing via an electrically insulating and mechanically elastic retaining device such that the connection element is moveable in the direction of passage, and wherein the spring element is arranged and designed in such a way that the spring action thereof acts directly or indirectly on the connection element in the direction of passage.

Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of a first length extending from a first surface of the substrate. An array of bump interconnects is disposed on the first surface. A die is interconnected to the substrate via the array of bump interconnects. A second bond via array includes second wires each of a second length different than the first length extending from a second surface of the die.

In some aspects, the techniques described herein relate to a semiconductor device including: a package including a plurality of pins; a semiconductor die including: a first bond pad; a second bond pad; and a pass transistor having: a drain terminal electrically coupled with the first bond pad; and a source terminal electrically coupled with the second bond pad; a first bond wire extending between a pin of the plurality of pins and the first bond pad; and a second bond wire extending between the pin and the second bond pad, the pass transistor being configured to facilitate detection of at least one of: lack of electrical continuity between the pin and the first bond pad; or lack of electrical continuity between the pin and the second bond pad.

Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

A power module includes: a plate-shaped thick copper substrate, a conductive stress relaxation metal layer disposed on the thick copper substrate, a semiconductor device disposed on the stress relaxation metal layer, and a plated layer disposed on the stress relaxation metal layer, wherein the semiconductor device is bonded to the stress relaxation metal layer via the plated layer. The thick copper substrate includes a first thick copper layer and a second thick copper layer disposed on the first thick copper layer, and the stress relaxation metal layer is disposed on the second thick copper layer. A part of the semiconductor device is embedded to be fixed to the stress relaxation metal layer. A bonded surface between the semiconductor device and the stress relaxation metal layer are integrated to each other by means of diffusion bonding or solid phase diffusion bonding.

A method and a device for establishing a wire connection between a first contact surface and at least one further contact surface. A contact end of a wire is positioned in a contact position relative to the first contact surface with a wire guiding tool. Subsequently, a mechanical, electrically conductive connection is established between the first contact surface and the contact end with a first solder material connection, and subsequently the wire guiding tool is moved to the further contact surface thus forming a wire section and establishing a further mechanical, electrically conductive connection between the wire section end and the further contact surface with a further solder material connection.

A charger includes a thermal conductive plate for heat dissipation, and a transistor. The transistor includes a drain terminal of a first pulsating voltage level, and a source terminal of a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. The source terminal is disposed closer to the thermal conductive plate than the drain terminal.

An upper conductor portion having a thickness A larger than a thickness B of a lower conductor portion, the upper conductor portion including a circuit pattern on which semiconductor chips are disposed and an outer peripheral pattern provided on an outer peripheral side of the circuit pattern at a certain gap, the outer peripheral pattern of the upper conductor portion, an outer peripheral portion of an insulating layer, and an outer peripheral portion of the lower conductor portion are fixed to a concave portion formed in the inner peripheral portion of the peripheral wall portion of a case, a collar portion projecting outward from the outer peripheral portion of the peripheral wall portion of the case is formed, and the attachment holes, through which the radiation fins are attachable, are formed in the collar portion.