According to one embodiment, a semiconductor device includes an integrated circuit (IC) chip and a silicon capacitor. The IC chip has a first terminal and a second terminal on a first surface. The silicon capacitor has a first electrode and a second electrode on a second surface facing the first surface. The first electrode is electrically connected to the first terminal through a first conductive member, and the second electrode is electrically connected to the second terminal through a second conductive member.

An apparatus is provided that includes a die stack having a first die and a second die disposed above a substrate, and a capacitor die disposed in the die stack between the first die and the second die. The capacitor die includes a plurality of integrated circuit capacitors that are configured to be selectively coupled together to form a desired capacitor value coupled to at least one of the first die and the second die.

The present disclosure includes: a base plate having a shape of a sheet; a relay plate having a shape of a sheet; a terminal member; and an electronic component joined to one surface of the base plate. The base plate, the relay plate, and the terminal member are electrically conductive members and arranged on a same plane with gaps between the electrically conductive members. The electronic component and one surface of the relay plate are connected to each other by a bonding wire. The one surface of the relay plate and one surface of the terminal member are connected to each other by a bonding wire.

According to one embodiment, a semiconductor device c includes: a package substrate including a base including a mount portion, and terminals; a semiconductor chip including a first pad to which a ground voltage is supplied, a second pad electrically connected to a first terminal among the terminals, and a semiconductor circuit connected to the first and second pads, the semiconductor chip being provided above the mount portion; and a first capacitor chip including a first capacitor unit provided in a silicon substrate, a first node supplied with the ground voltage, and a second node electrically connected to the second pad, the first capacitor chip being provided above the mount portion.

A semiconductor package includes: a package board including a plurality of connection pads; a semiconductor chip including a first surface and a plurality of bonding pads, wherein the first surface of the semiconductor chip contacts a first surface of the package board, and wherein the plurality of bonding pads are respectively connected to the plurality of connection pads; and a thermal fuse circuit connected between a sensing connection pad of the plurality of connection pads and a sensing bonding pad of the plurality of bonding pads, and configured to open between the sensing connection pad and the sensing bonding pad when an internal temperature of the thermal fuse circuit is greater than or equal to a cutoff temperature of the thermal fuse circuit.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.

A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.

A semiconductor module (10A) according to one embodiment includes: vertical first and second transistor chips (12A, 12B), wherein a second main electrode pad (20) formed on a back surface of the first transistor chip is mounted on and connected to a first wiring pattern (74) on the substrate, a first control electrode pad (16) formed together with a first main electrode pad on a front surface of the first transistor chip is electrically connected to a second wiring pattern (76) on the substrate, third main electrode pad (18) formed together with a second control electrode pad on a front surface of the second transistor is mounted on and connected to the first wiring pattern, and the second control electrode pad (16) formed on a back surface of the second transistor chip is electrically connected to a third wiring pattern.

Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna structure has a plurality of spacing members and at least one wire connected among the spacing members. No additional layout area is required to be formed on a surface of the carrier, such that the objective of miniaturization can be achieved.

A die is mounted in an integrated circuit package. The die includes a balun circuit and an electrostatic discharge (ESD) circuit coupled to a ground of the integrated circuit die. The package has a first output pin coupled to a first terminal of the balun and has a second output pin coupled to a second terminal of the balun through first and second bond wires. The second output pin is connected to board ground. A third bond wire is disposed between the second package terminal and the ESD circuit to provide a safe discharge path through the third bond wire for ESD events affecting the first and second output terminals. Thus, a charge that builds up involving one of the output terminals coupled to the balun can be safely dissipated.